~kris/9p

9hist

ref: fe99aed693000fbd49d33afc7ab14241bbb64ba3 9hist/bitsy/clock.c -rw-r--r-- 3.0 KiB
fe99aed6 — David du Colombier Plan 9 from Bell Labs 2002-05-06 24 years ago
                                                                                
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
#include	"u.h"
#include	"../port/lib.h"
#include	"mem.h"
#include	"dat.h"
#include	"fns.h"
#include	"io.h"
#include	"ureg.h"
#include	"../port/error.h"

typedef struct OSTimer
{
	ulong		osmr[4];	/* match registers */
	volatile ulong	oscr;		/* counter register */
	ulong		ossr;		/* status register */
	ulong		ower;	/* watchdog enable register */
	ulong		oier;		/* timer interrupt enable register */
} OSTimer;

OSTimer *timerregs = (OSTimer*)OSTIMERREGS;
static int clockinited;

static void		clockintr(Ureg*, void*);
static uvlong	when;	/* scheduled time of next interrupt */

long	timeradjust;

enum
{
	Minfreq = ClockFreq/HZ,		/* At least one interrupt per HZ (50 ms) */
	Maxfreq = ClockFreq/10000,	/* At most one interrupt every 100 µs */
};

void
clockpower(int on)
{

	if (on){
		timerregs->ossr |= 1<<0;
		timerregs->oier = 1<<0;
		timerregs->osmr[0] = timerregs->oscr + Minfreq;
	}
	clockinited = on;
}

void
clockinit(void)
{
	ulong x;
	ulong id;

	/* map the clock registers */
	timerregs = mapspecial(OSTIMERREGS, 32);

	/* enable interrupts on match register 0, turn off all others */
	timerregs->ossr |= 1<<0;
	intrenable(IRQ, IRQtimer0, clockintr, nil, "clock");
	timerregs->oier = 1<<0;

	/* figure out processor frequency */
	x = powerregs->ppcr & 0x1f;
	conf.hz = ClockFreq*(x*4+16);
	conf.mhz = (conf.hz+499999)/1000000;

	/* get processor type */
	id = getcpuid();

	print("%lud MHZ ARM, ver %lux/part %lux/step %lud\n", conf.mhz,
		(id>>16)&0xff, (id>>4)&0xfff, id&0xf);

	/* post interrupt 1/HZ secs from now */
	when = timerregs->oscr + Minfreq;
	timerregs->osmr[0] = when;

	timersinit();

	clockinited = 1;
}

/*  turn 32 bit counter into a 64 bit one.  since todfix calls
 *  us at least once a second and we overflow once every 1165
 *  seconds, we won't miss an overflow.
 */
uvlong
fastticks(uvlong *hz)
{
	static uvlong high;
	static ulong last;
	ulong x;

	if(hz != nil)
		*hz = ClockFreq;
	x = timerregs->oscr;
	if(x < last)
		high += 1LL<<32;
	last = x;
	return high+x;
}

void
timerset(uvlong v)
{
	ulong next, tics;	/* Must be unsigned! */
	static int count;

	next = v;

	/* post next interrupt: calculate # of tics from now */
	tics = next - timerregs->oscr - Maxfreq;
	if (tics > Minfreq){
		timeradjust++;
		next = timerregs->oscr + Maxfreq;
	}
	timerregs->osmr[0] = next;
}

static void
clockintr(Ureg *ureg, void*)
{
	/* reset previous interrupt */
	timerregs->ossr |= 1<<0;
	when += Minfreq;
	timerregs->osmr[0] = when;	/* insurance */

	timerintr(ureg, when);
}

void
delay(int ms)
{
	ulong start;
	int i;

	if(clockinited){
		while(ms-- > 0){
			start = timerregs->oscr;
			while(timerregs->oscr-start < ClockFreq/1000)
				;
		}
	} else {
		while(ms-- > 0){
			for(i = 0; i < 1000; i++)
				;
		}
	}
}

void
µdelay(ulong µs)
{
	ulong start;
	int i;

	µs++;
	if(clockinited){
		start = timerregs->oscr;
		while(timerregs->oscr - start < 1UL+(µs*ClockFreq)/1000000UL)
			;
	} else {
		while(µs-- > 0){
			for(i = 0; i < 10; i++)
				;
		}
	}
}

ulong
TK2MS(ulong ticks)
{
	uvlong t, hz;

	t = ticks;
	hz = HZ;
	t *= 1000L;
	t = t/hz;
	ticks = t;
	return ticks;
}