~kris/9p

9hist

fe51fb42d461fbb026b694e7f3be3bf96cf753ea — David du Colombier 25 years ago 900a42a
Plan 9 from Bell Labs 2000-10-27
6 files changed, 24 insertions(+), 69 deletions(-)

M bitsy/dat.h
M bitsy/fpiarm.c
M bitsy/main.c
M bitsy/trap.c
M pc/sdmylex.c
M port/proc.c
M bitsy/dat.h => bitsy/dat.h +3 -3
@@ 40,9 40,9 @@ struct Label
 */
enum
{
	FPINIT,
	FPACTIVE,
	FPINACTIVE,
	FPinit,
	FPactive,
	FPinactive,
};
struct	FPsave
{

M bitsy/fpiarm.c => bitsy/fpiarm.c +11 -19
@@ 15,14 15,12 @@

#include "fpi.h"

#define	R13OK
/* undef this if correct kernel r13 isn't in Ureg;
 * check calculation in fpiarm below
 */


#define	REG(x) (*(long*)(((char*)ur)+roff[(x)]))
#define	FPENV	(*ufp)
#define	FR(x) (*(Internal*)ufp->regs[(x)&7])

/* BUG: check fetch (not worthwhile in Inferno) */


@@ 51,7 49,7 @@ enum {
	REGPC = 15,
};

int	fpemudebug = 0;
int	fpemudebug = 1;

#undef OFR
#define	OFR(X)	((ulong)&((Ureg*)0)->X)


@@ 60,11 58,7 @@ static	int	roff[] = {
	OFR(r0), OFR(r1), OFR(r2), OFR(r3),
	OFR(r4), OFR(r5), OFR(r6), OFR(r7),
	OFR(r8), OFR(r9), OFR(r10), OFR(r11),
#ifdef R13OK
	OFR(r12), OFR(r13), OFR(r14), OFR(pc),
#else
	OFR(r12), OFR(type), OFR(r14), OFR(pc),
#endif
};

static Internal fpconst[8] = {	/* indexed by op&7 */


@@ 392,22 386,22 @@ fpemu(ulong pc, ulong op, Ureg *ur, FPsave *ufp)
				print("MOV[FD]W	F%d, R%d =%ld\n", rn, rd, REG(rd));
			break;
		case 2:	/* FPSR := Rd */
			FPENV.status = REG(rd);
			ufp->status = REG(rd);
			if(fpemudebug)
				print("MOVW	R%d, FPSR\n", rd);
			break;
		case 3:	/* Rd := FPSR */
			REG(rd) = FPENV.status;
			REG(rd) = ufp->status;
			if(fpemudebug)
				print("MOVW	FPSR, R%d\n", rd);
			break;
		case 4:	/* FPCR := Rd */
			FPENV.control = REG(rd);
			ufp->control = REG(rd);
			if(fpemudebug)
				print("MOVW	R%d, FPCR\n", rd);
			break;
		case 5:	/* Rd := FPCR */
			REG(rd) = FPENV.control;
			REG(rd) = ufp->control;
			if(fpemudebug)
				print("MOVW	FPCR, R%d\n", rd);
			break;


@@ 458,25 452,23 @@ fpiarm(Ureg *ur)
	FPsave *ufp;
	int n;

#ifndef R13OK
/*	ur->type = &ur->pc+1;	/* calculate kernel sp/R13 and put it here for roff[13] */
	ur->type = (ulong)(ur + 1);
#endif
	if (up == nil)
		panic("fpiarm not in a process");
	ufp = &up->fpsave;
		/* because all the state is in the proc structure,
		 * it need not be saved/restored
		 */
	if(up->fpstate != FPACTIVE) {
		up->fpstate = FPACTIVE;
	if(up->fpstate != FPactive) {
//		assert(sizeof(Internal) == sizeof(ufp->regs[0]));
		up->fpstate = FPactive;
		ufp->control = 0;
		ufp->status = (0x01<<28)|(1<<12);	/* software emulation, alternative C flag */
		for(n = 0; n < 8; n++)
			FR(n) = fpconst[0];
	}
	for(n=0;;n++){
		op = getulong(ur->pc);
	for(n=0; ;n++){
		validaddr(ur->pc, 4, 0);
		op = *(ulong*)(ur->pc);
		o = (op>>24) & 0xF;
		if(((op>>8) & 0xF) != 1 || o != 0xE && (o&~1) != 0xC)
			break;

M bitsy/main.c => bitsy/main.c +1 -1
@@ 229,7 229,7 @@ userinit(void)
void
procsetup(Proc *p)
{
	p->fpstate = FPINIT;
	p->fpstate = FPinit;
}

/*

M bitsy/trap.c => bitsy/trap.c +7 -36
@@ 265,52 265,23 @@ trap(Ureg *ureg)
		}
		break;
	case PsrMund:	/* undefined instruction */
#ifdef NOTDEF
		/* Inferno break handling, something for us? [SJM] */
		if(*(ulong*)ureg->pc == BREAK && breakhandler) {
			int s;
			Proc *p;

			p = up;
			/* if (!waslo(ureg->psr) || (ureg->pc >= (ulong)splhi && ureg->pc < (ulong)islo))
				p = 0; */
			s = breakhandler(ureg, p);
			if(s == BrkSched) {
				c.callsched = 1;
				sched();
			} else if(s == BrkNoSched) {
				c.callsched = 0;
				if(up)
					up->dbgreg = 0;
				return;
			}
			break;
		}
		/* End of Inferno break handling [SJM] */
#endif
		/* start of Inferno code [SJM] */
		spllo();
		if (waserror()) {
			warnregs(ureg, "floating point error");
			panic("floating point error");
		}
		if (!fpiarm(ureg)) {
			warnregs(ureg, "illegal instruction");
			panic("illegal instruction");
		}
		poperror();
		/* end of Inferno code [SJM] */
#ifdef NOTDEF
		/* We'll see what we do with this later [SJM] */
		if(user){
			sprint(buf, "undefined instruction: pc 0x%lux\n",
					ureg->pc);
			postnote(up, 1, buf, NDebug);
		if (user) {
			if (!fpiarm(ureg)) {
				sprint(buf, "undefined instruction: pc 0x%lux\n", ureg->pc);
				postnote(up, 1, buf, NDebug);
			}
		}else{
			warnregs(ureg, "undefined instruction");
			panic("undefined instruction");
		}
#endif
		poperror();
		/* end of Inferno code [SJM] */
		break;
	}


M pc/sdmylex.c => pc/sdmylex.c +1 -9
@@ 630,17 630,9 @@ mylex32rio(SDreq* r)
	 */
	while(waserror())
		;
	tsleep(ccb, done32, ccb, 30*1000);
	sleep(ccb, done32, ccb);
	poperror();

	if(!done32(ccb)){
		print("%s: %d/%d: sd32rio timeout\n",
			ctlr->sdev->name, target, r->lun);
		ccbfree(ctlr, (Ccb*)ccb);

		return SDtimeout;
	}

	/*
	 * Save the status and patch up the number of
	 * bytes actually transferred.

M port/proc.c => port/proc.c +1 -1
@@ 327,7 327,7 @@ newproc(void)
	p->fgrp = 0;
	p->rgrp = 0;
	p->pdbg = 0;
	p->fpstate = FPINIT;
	p->fpstate = FPinit;
	p->kp = 0;
	p->procctl = 0;
	p->notepending = 0;