8 files changed, 110 insertions(+), 31 deletions(-)

M bitsy/dat.h
M bitsy/devuart.c
M bitsy/io.h
M bitsy/main.c
M bitsy/mem.h
M bitsy/mmu.c
M pc/devarch.c
M pc/etherelnk3.c

@@ 178,3 178,8 @@ Mach* machp[MAXMACH];
 
 extern Mach	*m;
 #define up	(((Mach*)MACHADDR)->externup)
+
+enum
+{
+	OneMeg=	1024*1024,
+};

@@ 15,7 15,6 @@ enum
 };
 
 /* hardware registers */
-typedef struct Uartregs Uartregs;
 struct Uartregs
 {
 	ulong	ctl0;


@@ 29,7 28,7 @@ struct Uartregs
 	ulong	status1;
 };
 
-static Uartregs *uart3regs = UART3REGS;
+Uartregs *uart3regs = UART3REGS;
 
 /* ctl0 bits */
 enum

@@ 1,3 1,5 @@
 /*
  *  Definitions for IO devices.  Used only in C.
  */
+typedef struct Uartregs Uartregs;
+Uartregs *uart3regs;

@@ 62,11 62,6 @@ rdb(void)
 {
 }
 
-enum
-{
-	OneMeg=	1024*1024,
-};
-
 /*
  *  probe the last location in a meg of memory, make sure it's not
  *  reflected into something else we've already found.

@@ 46,6 46,7 @@
 #define	KZERO		0xC0000000		/* base of kernel address space */
 #define	KTZERO		0xC0008000		/* first address in kernel text */
 #define	REGZERO		0xA0000000		/* 256 meg for special regs */
+#define	REGTOP		0xB0000000		/* 256 meg for special regs */
 #define	FLASHZERO	0xB0000000		/* 256 meg for flash */
 #define	USTKTOP		(REGZERO-BY2PG)		/* byte just beyond user stack */
 #define	USTKSIZE	(16*1024*1024)		/* size of user stack */


@@ 172,6 173,7 @@
 #define	PTERONLY	0	/* this is implied by the absence of PTEWRITE */
 #define	PTEWRITE	(1<<1)
 #define	PTEUNCACHED	(1<<2)
+#define PTEKERNEL	(1<<3)	/* no user access */
 
 /*
  *  H3650 specific definitions

@@ 10,28 10,49 @@
 /* real protection bits */
 enum
 {
-	Small_Page=	(2<<0),
-	Large_Page=	(1<<0),
-	Cached=		(1<<3),
-	Buffered=	(1<<2),
-	UserRO=		(0xAA<<4),
-	UserRW=		(0xFF<<4),
-	KernelRW=	(0x55<<4),
+	/* level 1 descriptor bits */
+	L1TypeMask=	(3<<0),
+	L1Invalid=	(0<<0),
+	L1PageTable=	(1<<0),
+	L1Section=	(2<<0),
+	L1Cached=	(1<<3),
+	L1Buffered=	(1<<2),
+	L1Domain0=	(0<<5),
+	L1KernelRW=	(0x1<<10),
+	L1UserRO=	(0x2<<10),
+	L1UserRW=	(0x3<<10),
+	L1SectBaseMask=	(0xFFF<<20),
+	L1PTBaseMask=	(0x3FFFFF<<10),
+	
+	/* level 2 descriptor bits */
+	L2TypeMask=	(3<<0),
+	L2SmallPage=	(2<<0),
+	L2LargePage=	(1<<0),
+	L2Cached=	(1<<3),
+	L2Buffered=	(1<<2),
+	L2KernelRW=	(0x55<<4),
+	L2UserRO=	(0xAA<<4),
+	L2UserRW=	(0xFF<<4),
+	L2PageBaseMask=	(0xFFFFF<<12),
 };
 
-
 /*
  *  table to map fault.c bits to physical bits
  */
-static ulong phystrans[8] =
+static ulong phystrans[16] =
 {
-	[PTEVALID]			Small_Page|Cached|Buffered|UserRO,
-	[PTEVALID|PTEWRITE]		Small_Page|Cached|Buffered|UserRW,
-	[PTEVALID|UNCACHED]		Small_Page|UserRO,
-	[PTEVALID|UNCACHED|PTEWRITE]	Small_Page|UserRW,
+	[PTEVALID]				L2SmallPage|L2Cached|L2Buffered|L2UserRO,
+	[PTEVALID|PTEWRITE]			L2SmallPage|L2Cached|L2Buffered|L2UserRW,
+	[PTEVALID|PTEUNCACHED]			L2SmallPage|L2UserRO,
+	[PTEVALID|PTEUNCACHED|PTEWRITE]		L2SmallPage|L2UserRW,
+
+	[PTEKERNEL|PTEVALID]			L2SmallPage|L2Cached|L2Buffered|L2KernelRW,
+	[PTEKERNEL|PTEVALID|PTEWRITE]		L2SmallPage|L2Cached|L2Buffered|L2KernelRW,
+	[PTEKERNEL|PTEVALID|PTEUNCACHED]		L2SmallPage|L2KernelRW,
+	[PTEKERNEL|PTEVALID|PTEUNCACHED|PTEWRITE]	L2SmallPage|L2KernelRW,
 };
 
-ulong *l1page;
+ulong *l1table;
 
 /*
  *  We map all of memory, flash, and the zeros area with sections.


@@ 46,14 67,57 @@ mmuinit(void)
 	putdac(0x55555555);
 
 	/* get a prototype level 1 page */
-	l1page = xspanalloc(BY2PG, 16*1024, 0);
-	memset(l1page, 0, BY2PG);
-
-	/* map DRAM */
-	e = PHYSDRAM0 + BY2PG*con
-	for(
-	/* map zeros */
-	/* map flash */
+	l1table = xspanalloc(BY2PG, 16*1024, 0);
+	memset(l1table, 0, BY2PG);
+
+	/* direct map DRAM */
+	e = conf.base1 + BY2PG*conf.npage2;
+	for(a = PHYSDRAM0; a < e; a += OneMeg)
+		l1table[a>>20] = L1Section | L1KernelRW |
+				L1Cached | L1Buffered | (a&L1SectBaseMask);
+
+	/* direct map zeros area */
+	for(a = PHYSNULL0; a < PHYSNULL0 + 128 * OneMeg; a += OneMeg)
+		l1table[a>>20] = L1Section | L1KernelRW |
+				L1Cached | L1Buffered | (a&L1SectBaseMask);
+
+	/* direct map flash */
+	for(a = PHYFLASH0; a < PHYFLASH0 + 128 * OneMeg; a += OneMeg)
+		l1table[a>>20] = L1Section | L1KernelRW |
+				L1Cached | L1Buffered | (a&L1SectBaseMask);
+
+	/* map the uart so that we can continue using iprint */
+	uart3regs = mapspecial(UART3REGS, 64);
+}
+
+/*
+ *  map special use space 
+ */
+ulong*
+mapspecial(ulong addr, int len)
+{
+	ulong *t;
+	ulong a, i;
+
+	/* first see if we've mapped it somewhere, the first hole means we're done */
+	for(a = REGZERO; a < REGTOP; a += OneMeg){
+		if((l1table[a>>20] & L1TypeMask) != L1PageTable){
+			/* create a page table and break */
+			t = xspanalloc(BY2PG, 1024, 0);
+			memzero(t, BY2PG, 0);
+			l1table[a>>20] = L1PageTable | L1Domain0 | (((ulong)t) & L1PTBaseMask);
+			break;
+		}
+		t = (ulong*)(l1table[a>>20] & L1PTBaseMask);
+		for(i = 0; i < OneMeg; i += BY2PG){
+			if((t[a>>20] & L2TypeMask) != L2SmallPage)
+				break;
+		}
+		if(i < OneMeg){
+			a += i;
+			break;
+		}
+	}
 }
 
 void

@@ 452,6 452,16 @@ static X86type x86amd[] =
 	{ -1,	-1,	23,	"unknown", },	/* total default */
 };
 
+/*
+ * WinChip 240MHz
+ */
+static X86type x86winchip[] =
+{
+	{5,	4,	23,	"Winchip",},	/* guesswork */
+	{ -1,	-1,	23,	"unknown", },	/* total default */
+};
+
+
 static uvlong fasthz;
 static X86type *cputype;
 


@@ 480,6 490,8 @@ cpuidentify(void)
 	cpuid(m->cpuidid, &m->cpuidax, &m->cpuiddx);
 	if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0)
 		t = x86amd;
+	else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
+		t = x86winchip;
 	else
 		t = x86intel;
 	family = X86FAMILY(m->cpuidax);

@@ 1811,9 1811,9 @@ etherelnk3reset(Ether* ether)
 /*
  * forgive me, but i am weak
  */
-if(did == 0x9055 || did ==0x9200){
+if(did == 0x9055 || did == 0x9200){
    xcvr = xcvrMii;
-   XCVRDEBUG("9055 reset ops 0x%uX\n",
+   XCVRDEBUG("905[BC] reset ops 0x%uX\n",
 	ins(port+ResetOp905B));
 }
 else