10 files changed, 192 insertions(+), 59 deletions(-)

M bitsy/devuart.c
M bitsy/fns.h
M bitsy/io.h
M bitsy/l.s
M bitsy/main.c
M bitsy/mem.h
M bitsy/mmu.c
M pc/sd53c8xx.c
M pc/sdmylex.c
M pc/vgamach64xx.c

@@ 28,7 28,8 @@ struct Uartregs
 	ulong	status0;
 	ulong	status1;
 };
-#define	UART3REGS IOA(Uartregs, 0x50000)
+
+static Uartregs *uart3regs = UART3REGS;
 
 /* ctl0 bits */
 enum


@@ 497,7 498,7 @@ serialputs(char *str, int n)
 {
 	Uartregs *ur;
 
-	ur = UART3REGS;
+	ur = uart3regs;
 	while(n-- > 0){
 		/* wait for output ready */
 		while((ur->status1 & XmitNotFull) == 0)

@@ 8,6 8,8 @@ void	clockintrsched(void);
 void	(*coherence)(void);
 void	delay(int);
 void	evenaddr(ulong);
+ulong	getfar(void);
+ulong	getfsr(void);
 #define	getpgcolor(a)	0
 void	idle(void);
 #define	idlehands()			/* nothing to do in the runproc */


@@ 17,7 19,9 @@ void	mmuinit(void);
 #define	procrestore(p)
 void	procsave(Proc*);
 void	procsetup(Proc*);
-void	putuartstr(char*);
+void	putdac(ulong);
+void	putttb(ulong);
+void	putpid(ulong);
 void	screeninit(void);
 int	screenprint(char*, ...);			/* debugging */
 void	(*screenputs)(char*, int);


@@ 29,6 33,6 @@ void	wbflush(void);
 
 #define	waserror()	(up->nerrlab++, setlabel(&up->errlab[up->nerrlab-1]))
 #define KADDR(a)	((void*)((ulong)(a)|KZERO))
-#define PADDR(a)	((ulong)(a)&~KZERO)
+#define PADDR(a)	((ulong)(a))
 
 #define	dcflush(a, b)

@@ 1,5 1,3 @@
 /*
- *  all register offsets are relative to 0x8000000 so that
- *  IOZERO can be changed at some future point
+ *  Definitions for IO devices.  Used only in C.
  */
-#define IOA(t, x)	((t*)(IOZERO|x))

@@ 1,6 1,4 @@
 #include "mem.h"
-#include "sa1110.h"
-#include "io.h"
 
 /*
  * Entered here from Compaq's bootldr with MMU disabled.


@@ 87,9 85,17 @@ TEXT getfar(SB), $-4
 	RET
 
 /* set the translation table base */
-TEXT setttb(SB), $-4
+TEXT putttb(SB), $-4
 	MCR	CpMMU, 0, R0, C(CpTTB), C(0x0)
 
+/* set the translation table base */
+TEXT putdac(SB), $-4
+	MCR	CpMMU, 0, R0, C(CpDAC), C(0x0)
+
+/* set the translation table base */
+TEXT putpid(SB), $-4
+	MCR	CpMMU, 0, R0, C(CpPID), C(0x0)
+
 /*
  *  set the stack value for the mode passed in R0
  */

@@ 8,8 8,6 @@
 #include	"init.h"
 #include	"pool.h"
 
-#include	"sa1110.h"
-
 Mach *m;
 Conf conf;
 


@@ 18,6 16,7 @@ main(void)
 {
 	iprint("bitsy kernel\n");
 	confinit();
+	xinit();
 	mmuinit();
 }
 

@@ 28,34 28,30 @@
 #define	MS2TK(t)	((((ulong)(t))*HZ)/1000)	/* milliseconds to ticks */
 
 /*
- * Fundamental addresses
- */
-#define MACHADDR	(KZERO+0x00001000)
-
-/*
- *  Address spaces:
+ *  Virtual addresses:
+ *
+ *  We direct map all discovered DRAM and the area twixt 0xe0000000 and
+ *  0xe8000000 used to provide zeros for cache flushing.
  *
- *  We've direct mapped the DRAM's and all the
- *  special use space.  Since the DRAM's lie at
- *  0xc0000000 and since the Compaq boot loader
- *  copies the kernel to the start of DRAM, we've
- *  made KZERO 0xc0000000.  We've also direct mapped
- *  the special use io space between 0x8000000 and KZERO.
- *  That means we can leave the MMU off till we're pretty
- *  far into the boot.
+ *  Flash is mapped to 0xb0000000 and special registers are mapped
+ *  on demand to areas starting at 0xa0000000.
  *
- *  Both these decisions can be changed by putting an MMU setup in
- *  l.s and changing the definitions below.
+ *  The direct mapping is convenient but not necessary.  It means
+ *  that we don't have to turn on the MMU till well into the
+ *  kernel.  This can be changed by providing a mapping in l.s
+ *  before calling main.
  */
 #define	UZERO		0			/* base of user address space */
 #define	UTZERO		(UZERO+BY2PG)		/* first address in user text */
 #define	KZERO		0xC0000000		/* base of kernel address space */
 #define	KTZERO		0xC0008000		/* first address in kernel text */
-#define	IOZERO		0x80000000		/* 1 gig of special regs */
-#define	USTKTOP		(IOZERO-BY2PG)		/* byte just beyond user stack */
+#define	REGZERO		0xA0000000		/* 256 meg for special regs */
+#define	FLASHZERO	0xB0000000		/* 256 meg for flash */
+#define	USTKTOP		(REGZERO-BY2PG)		/* byte just beyond user stack */
 #define	USTKSIZE	(16*1024*1024)		/* size of user stack */
 #define	TSTKTOP		(USTKTOP-USTKSIZE)	/* end of new stack in sysexec */
 #define TSTKSIZ 	100
+#define MACHADDR	(KZERO+0x00001000)
 
 #define KSTACK		(16*1024)		/* Size of kernel stack */
 


@@ 69,10 65,115 @@
 #define PPN(x)		((x)&~(BY2PG-1))
 
 /*
- *  physical MMU
+ *  SA1110 definitions
+ */
+
+/*
+ *  memory physical addresses
+ */
+#define PHYSFLASH0	0x00000000
+#define PHYSDRAM0	0xC0000000
+#define	PHYSNULL0	0xE0000000
+
+/*
+ *  peripheral control module physical addresses
+ */
+#define LCDREGS		0xB0100000	/* display */
+#define USBREGS		0x80000000	/* serial port 0 - USB */
+#define UART1REGS	0x80010000	/* serial port 1 - UART */
+#define GPCLKREGS	0x80020060	/* serial port 1 - general purpose clock */
+#define UART2REGS	0x80030000	/* serial port 2 - low speed IR */
+#define HSSPREGS	0x80040060	/* serial port 2 - high speed IR */
+#define UART3REGS	0x80050000	/* serial port 3 - RS232 UART */
+#define MCPREGS		0x80060000	/* serial port 4 - multimedia comm port */
+#define SSPREGS		0x80070060	/* serial port 4 - synchronous serial port */
+#define PPCREGS		0x90060000	/* peripheral pin controller */
+#define GPIOREGS	0x90040000	/* 28 general purpose IO pins */
+
+/*
+ *  Program Status Registers
+ */
+#define PsrMusr		0x00000010	/* mode */
+#define PsrMfiq		0x00000011
+#define PsrMirq		0x00000012
+#define PsrMsvc		0x00000013
+#define PsrMabt		0x00000017
+#define PsrMund		0x0000001B
+#define PsrMask		0x0000001F
+
+#define PsrDfiq		0x00000040	/* disable FIQ interrupts */
+#define PsrDirq		0x00000080	/* disable IRQ interrupts */
+
+#define PsrV		0x10000000	/* overflow */
+#define PsrC		0x20000000	/* carry/borrow/extend */
+#define PsrZ		0x40000000	/* zero */
+#define PsrN		0x80000000	/* negative/less than */
+
+/*
+ *  Coprocessors
+ */
+#define CpMMU		15
+
+/*
+ *  Internal MMU coprocessor registers
+ */
+#define CpCPUID		0		/* R: */
+#define CpControl	1		/* R: */
+#define CpTTB		2		/* RW: translation table base */
+#define CpDAC		3		/* RW: domain access control */
+#define CpFSR		5		/* RW: fault status */
+#define CpFAR		6		/* RW: fault address */
+#define CpCacheFlush	7		/* W: cache flushing, wb draining*/
+#define CpTLBFlush	8		/* W: TLB flushing */
+#define CpRBFlush	9		/* W: Read Buffer ops */
+#define CpPID		13		/* RW: PID for virtual mapping */
+#define	CpBpt		14		/* W: Breakpoint register */
+#define CpTest		15		/* W: Test, CLock and Idle Control */
+
+/*
+ *  CpControl
  */
-#define	PTEVALID	0
-#define	PTERONLY	0
-#define	PTEWRITE	0
-#define	PTEUNCACHED	0
+#define CpCmmu		0x00000001	/* M: MMU enable */
+#define CpCalign	0x00000002	/* A: alignment fault enable */
+#define CpCdcache	0x00000004	/* C: data cache on */
+#define CpCwb		0x00000008	/* W: write buffer turned on */
+#define CpCi32		0x00000010	/* P: 32-bit program space */
+#define CpCd32		0x00000020	/* D: 32-bit data space */
+#define CpCbe		0x00000080	/* B: big-endian operation */
+#define CpCsystem	0x00000100	/* S: system permission */
+#define CpCrom		0x00000200	/* R: ROM permission */
+#define CpCicache	0x00001000	/* I: instruction cache on */
+#define CpCvivec	0x00002000	/* X: virtual interrupt vector adjust */
 
+/*
+ *  fault codes
+ */
+#define	FCterm		0x2	/* terminal */
+#define	FCvec		0x0	/* vector */
+#define	FCalignf	0x1	/* unaligned full word data access */
+#define	FCalignh	0x3	/* unaligned half word data access */
+#define	FCl1abort	0xc	/* level 1 external abort on translation */
+#define	FCl2abort	0xe	/* level 2 external abort on translation */
+#define	FCtransSec	0x5	/* section translation */
+#define	FCtransPage	0x7	/* page translation */
+#define	FCdomainSec	0x9	/* section domain  */
+#define	FCdomainPage	0x11	/* page domain */
+#define	FCpermSec	0x9	/* section permissions  */
+#define	FCpermPage	0x11	/* page permissions */
+#define	FCabortLFSec	0x4	/* external abort on linefetch for section */
+#define	FCabortLFPage	0x6	/* external abort on linefetch for page */
+#define	FCabortNLFSec	0x8	/* external abort on non-linefetch for section */
+#define	FCabortNLFPage	0xa	/* external abort on non-linefetch for page */
+
+/*
+ *  PTE bits used by fault.h.  mmu.c translates them to real values.
+ */
+#define	PTEVALID	(1<<0)
+#define	PTERONLY	0	/* this is implied by the absence of PTEWRITE */
+#define	PTEWRITE	(1<<1)
+#define	PTEUNCACHED	(1<<2)
+
+/*
+ *  H3650 specific definitions
+ */
+#define EGPIOREGS	0x49000000	/* Additional GPIO register */

@@ 7,9 7,53 @@
 #include	"ureg.h"
 #include	"../port/error.h"
 
+/* real protection bits */
+enum
+{
+	Small_Page=	(2<<0),
+	Large_Page=	(1<<0),
+	Cached=		(1<<3),
+	Buffered=	(1<<2),
+	UserRO=		(0xAA<<4),
+	UserRW=		(0xFF<<4),
+	KernelRW=	(0x55<<4),
+};
+
+
+/*
+ *  table to map fault.c bits to physical bits
+ */
+static ulong phystrans[8] =
+{
+	[PTEVALID]			Small_Page|Cached|Buffered|UserRO,
+	[PTEVALID|PTEWRITE]		Small_Page|Cached|Buffered|UserRW,
+	[PTEVALID|UNCACHED]		Small_Page|UserRO,
+	[PTEVALID|UNCACHED|PTEWRITE]	Small_Page|UserRW,
+};
+
+ulong *l1page;
+
+/*
+ *  We map all of memory, flash, and the zeros area with sections.
+ *  Special use space is mapped on the fly with regmap.
+ */
 void
 mmuinit(void)
 {
+	ulong a, e;
+
+	/* set up the domain register to cause all domains to obey pte access bits */
+	putdac(0x55555555);
+
+	/* get a prototype level 1 page */
+	l1page = xspanalloc(BY2PG, 16*1024, 0);
+	memset(l1page, 0, BY2PG);
+
+	/* map DRAM */
+	e = PHYSDRAM0 + BY2PG*con
+	for(
+	/* map zeros */
+	/* map flash */
 }
 
 void

@@ 1732,19 1732,9 @@ docheck:
 
 	while(waserror())
 		;
-	tsleep(d, done, d, 30 * 1000);
+	sleep(d, done, d);
 	poperror();
 
-	if (!done(d)) {
-		KPRINT(PRINTPREFIX "%d/%d: exec: Timed out\n", target, r->lun);
-		dumpncrregs(c, 0);
-		dsafree(c, d);
-		reset(c);
-		qunlock(&c->q[target]);
-		r->status = SDtimeout;
-		return r->status = SDtimeout;	/* assign */
-	}
-
 	if((status = d->p9status) == SDeio)
 		c->s[target] = NeitherDone;
 	if (d->parityerror) {

@@ 409,21 409,9 @@ mylex24rio(SDreq* r)
 	 */
 	while(waserror())
 		;
-	tsleep(ccb, done24, ccb, 30*1000);
+	sleep(ccb, done24, ccb);
 	poperror();
 
-	if(!done24(ccb)){
-		print("%s: %d/%d: sd24rio timeout\n",
-			ctlr->sdev->name, target, r->lun);
-		if(ccb->data != nil){
-			free(data);
-			ccb->data = nil;
-		}
-		ccbfree(ctlr, (Ccb*)ccb);
-
-		return SDtimeout;
-	}
-
 	/*
 	 * Save the status and patch up the number of
 	 * bytes actually transferred.

@@ 21,6 21,7 @@ static ushort mach64xxdid[] = {
 	('G'<<8)|'B',
 	('G'<<8)|'D',
 	('G'<<8)|'I',
+	('G'<<8)|'M',
 	('G'<<8)|'P',
 	('G'<<8)|'Q',
 	('G'<<8)|'T',


@@ 799,3 800,4 @@ VGAcur vgamach64xxcur = {
 
 	1					/* doespanning */
 };
+