M boot/boot.c => boot/boot.c +6 -4
@@ 44,16 44,18 @@ boot(int argc, char *argv[])
char buf[32];
AuthInfo *ai;
- sleep(1000);
-
-
fmtinstall('r', rconv);
open("#c/cons", OREAD);
open("#c/cons", OWRITE);
open("#c/cons", OWRITE);
bind("#c", "/dev", MAFTER);
- bind("#e", "/env", MREPL|MCREATE);
+ /*
+ * init will reinitialize its namespace.
+ * #ec gets us plan9.ini settings.
+ */
+ bind("#ec", "/env", MREPL|MCREATE);
+ bind("#e", "/env", MAFTER);
bind("#s", "/srv", MREPL|MCREATE);
#ifdef DEBUG
M mtx/devether.c => mtx/devether.c +1 -1
@@ 377,7 377,7 @@ etherreset(void)
* controllers together. A device set to IRQ2 will appear on
* the second interrupt controller as IRQ9.
*/
- if(ether->irq == 2)
+ if(ether->irq == 2 && BUSTYPE(ether->tbdf) != BusPCI)
ether->irq = 9;
snprint(name, sizeof(name), "ether%d", ctlrno);
M mtx/ether2114x.c => mtx/ether2114x.c +5 -5
@@ 19,7 19,7 @@
#include "etherif.h"
-#define DEBUG (1)
+#define DEBUG (0)
#define debug if(DEBUG)print
enum {
@@ 56,7 56,7 @@ enum { /* CSR[57] - Status and Interrupt Enable */
Rwt = 0x00000200, /* Receive Watchdog Timeout */
Eti = 0x00000400, /* Early Transmit Interrupt */
Gte = 0x00000800, /* General purpose Timer Expired */
- Fbe = 0x00002000, /* Fatal Bit Error */
+ Fbe = 0x00002000, /* Fatal Bus Error */
Ais = 0x00008000, /* Abnormal Interrupt Summary */
Nis = 0x00010000, /* Normal Interrupt Summary */
Rs = 0x000E0000, /* Receive process State (field) */
@@ 419,7 419,6 @@ interrupt(Ureg*, void* arg)
Des *des;
Block *bp;
-print("ether intr\n");
ether = arg;
ctlr = ether->ctlr;
@@ 800,7 799,7 @@ softreset(Ctlr* ctlr)
*/
csr32w(ctlr, 0, Swr);
microdelay(10);
- csr32w(ctlr, 0, Rml|Cal16);
+ csr32w(ctlr, 0, Rml|Cal16|Dbo);
delay(1);
}
@@ 1596,7 1595,8 @@ reset(Ether* ether)
ether->ctlr = ctlr;
ether->port = ctlr->port;
- ether->irq = ctlr->pcidev->intl;
+// ether->irq = ctlr->pcidev->intl;
+ether->irq = 2; /* arrrrrgh */
ether->tbdf = ctlr->pcidev->tbdf;
/*
M mtx/io.h => mtx/io.h +1 -1
@@ 180,5 180,5 @@ typedef struct Pcidev {
ulong pcr;
};
-#define PCIWINDOW 0
+#define PCIWINDOW 0x80000000
#define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
M mtx/main.c => mtx/main.c +75 -10
@@ 260,11 260,15 @@ procsave(Proc *p)
void
confinit(void)
{
- ulong pa;
+ char *p;
+ int userpcnt;
+ ulong pa, kpages;
extern ulong memsize; /* passed in from ROM monitor */
- conf.nmach = 1; /* processors */
- conf.nproc = 60; /* processes */
+ if(p = getconf("*kernelpercent"))
+ userpcnt = 100 - strtol(p, 0, 0);
+ else
+ userpcnt = 0;
pa = PGROUND(PADDR(end));
@@ 276,15 280,76 @@ confinit(void)
conf.npage = conf.npage0 + conf.npage1;
- conf.upages = (conf.npage*60)/100;
- conf.ialloc = ((conf.npage-conf.upages)/2)*BY2PG;
+ conf.nmach = 1;
+ conf.nproc = 100 + ((conf.npage*BY2PG)/MB)*5;
+ if(cpuserver)
+ conf.nproc *= 3;
+ if(conf.nproc > 2000)
+ conf.nproc = 2000;
+ conf.nimage = 200;
+ conf.nswap = conf.nproc*80;
+ conf.nswppo = 4096;
+ conf.copymode = 0; /* copy on write */
+
+ if(cpuserver) {
+ if(userpcnt < 10)
+ userpcnt = 70;
+ kpages = conf.npage - (conf.npage*userpcnt)/100;
+
+ /*
+ * Hack for the big boys. Only good while physmem < 4GB.
+ * Give the kernel a max. of 16MB + enough to allocate the
+ * page pool.
+ * This is an overestimate as conf.upages < conf.npages.
+ * The patch of nimage is a band-aid, scanning the whole
+ * page list in imagereclaim just takes too long.
+ */
+ if(kpages > (16*MB + conf.npage*sizeof(Page))/BY2PG){
+ kpages = (16*MB + conf.npage*sizeof(Page))/BY2PG;
+ conf.nimage = 2000;
+ kpages += (conf.nproc*KSTACK)/BY2PG;
+ }
+ } else {
+ if(userpcnt < 10) {
+ if(conf.npage*BY2PG < 16*MB)
+ userpcnt = 40;
+ else
+ userpcnt = 60;
+ }
+ kpages = conf.npage - (conf.npage*userpcnt)/100;
+
+ /*
+ * Make sure terminals with low memory get at least
+ * 4MB on the first Image chunk allocation.
+ */
+ if(conf.npage*BY2PG < 16*MB)
+ imagmem->minarena = 4*1024*1024;
+ }
+ conf.upages = conf.npage - kpages;
+ conf.ialloc = (kpages/2)*BY2PG;
- /* set up other configuration parameters */
- conf.nswap = 0;
- conf.nswppo = 0;
- conf.nimage = 20;
+ /*
+ * Guess how much is taken by the large permanent
+ * datastructures. Mntcache and Mntrpc are not accounted for
+ * (probably ~300KB).
+ */
+ kpages *= BY2PG;
+ kpages -= conf.upages*sizeof(Page)
+ + conf.nproc*sizeof(Proc)
+ + conf.nimage*sizeof(Image)
+ + conf.nswap
+ + conf.nswppo*sizeof(Page);
+ mainmem->maxsize = kpages;
+ if(!cpuserver){
+ /*
+ * give terminals lots of image memory, too; the dynamic
+ * allocation will balance the load properly, hopefully.
+ * be careful with 32-bit overflow.
+ */
+ imagmem->maxsize = kpages;
+ }
- conf.copymode = 0; /* copy on write */
+// conf.monitor = 1; /* BUG */
}
static int
M mtx/trap.c => mtx/trap.c +0 -3
@@ 24,7 24,6 @@ hwintrenable(Vctl *v)
irq = v->irq;
if(BUSTYPE(v->tbdf) == BusPCI) { /* MPIC? */
-print("add PCI intr %d\n", irq);
if(irq > 15) {
print("intrenable: pci irq %d out of range\n", v->irq);
return -1;
@@ 33,7 32,6 @@ print("add PCI intr %d\n", irq);
mpicenable(vec, v);
}
else {
-print("add pic intr %d\n", irq);
if(irq > MaxIrqPIC) {
print("intrenable: irq %d out of range\n", v->irq);
return -1;
@@ 350,7 348,6 @@ intr(Ureg *ureg)
vno = i8259intack();
mpiceoi(0);
}
-else print("non-pic %d\n", vno);
if(vno > nelem(vctl) || (ctl = vctl[vno]) == 0) {
panic("spurious intr %d", vno);
M pc/devi82365.c => pc/devi82365.c +4 -2
@@ 1007,9 1007,11 @@ pcmio(int slotno, ISAConf *isa)
m = pcmmap(slotno, pp->caddr + Rconfig, 1, 1);
p = KADDR(m->isa + pp->caddr + Rconfig - m->ca);
- /* set configuration and interrupt type */
+ /* set configuration and interrupt type.
+ * if level is possible on the card, use it.
+ */
x = ct->index;
- if((ct->irqtype & 0x20) && ((ct->irqtype & 0x40)==0 || isa->irq>7))
+ if(ct->irqtype & 0x20)
x |= Clevel;
*p = x;
delay(5);
M pc/devpccard.c => pc/devpccard.c +1 -1
@@ 1059,7 1059,7 @@ pccard_pcmspecial(char *idstr, ISAConf *isa)
/* set configuration and interrupt type */
x = ct->index;
- if((ct->irqtype & 0x20) && ((ct->irqtype & 0x40)==0 || isa->irq>7))
+ if(ct->irqtype & 0x20)
x |= Clevel;
*p = x;
delay(5);