~kris/9p

9hist

26f6aec4c1cb01e685cbdd6e0cd5209ae65a3264 — David du Colombier 32 years ago c861cdf
Plan 9 from Bell Labs 1993-12-31
3 files changed, 29 insertions(+), 39 deletions(-)

M carrera/devether.c
M carrera/l.s
M port/alloc.c
M carrera/devether.c => carrera/devether.c +1 -6
@@ 563,7 563,7 @@ initbufs(Ether *c)
	int i;
	uchar *mem, *base;

	mem = xspanalloc(64*1024, BY2PG, 0);
	mem = xspanalloc(64*1024, 8, 64*1024);
	base = mem;
	mem = CACHELINE(uchar, mem);



@@ 581,12 581,7 @@ initbufs(Ether *c)

	c->cda = UNCACHED(Cam, mem);

	/*
	 * DMA buffers are cache coherent - but we must not straddle
	 * a cache line
	 */
	mem = CACHELINE(uchar, mem+sizeof(Cam));

	for(i = 0; i < Nrb; i++) {
		c->rb[i] = UNCACHED(uchar, mem);
		mem += sizeof(Pbuf)+4;

M carrera/l.s => carrera/l.s +8 -8
@@ 742,9 742,9 @@ TEXT	icflush(SB), $-4			/* icflush(virtaddr, count) */
	ADDU	R1, R9			/* R9 = last address */
	MOVW	$(~0x3f), R8
	AND	R1, R8			/* R8 = first address, rounded down */
	ADD	$0x3f, R9
	ADDU	$0x3f, R9
	AND	$(~0x3f), R9		/* round last address up */
	SUB	R8, R9			/* R9 = revised count */
	SUBU	R8, R9			/* R9 = revised count */
icflush1:			/* primary cache line size is 16 bytes */
	CACHE	PD+HWB, 0x00(R8)
	CACHE	PI+HI, 0x00(R8)


@@ 754,8 754,8 @@ icflush1:			/* primary cache line size is 16 bytes */
	CACHE	PI+HI, 0x20(R8)
	CACHE	PD+HWB, 0x30(R8)
	CACHE	PI+HI, 0x30(R8)
	SUB	$0x40, R9
	ADD	$0x40, R8
	SUBU	$0x40, R9
	ADDU	$0x40, R8
	BGTZ	R9, icflush1
	MOVW	R10, M(STATUS)
	WAIT


@@ 773,9 773,9 @@ TEXT	dcflush(SB), $-4			/* dcflush(virtaddr, count) */
	ADDU	R1, R9			/* R9 = last address */
	MOVW	$(~0x3f), R8
	AND	R1, R8			/* R8 = first address, rounded down */
	ADD	$0x3f, R9
	ADDU	$0x3f, R9
	AND	$(~0x3f), R9		/* round last address up */
	SUB	R8, R9			/* R9 = revised count */
	SUBU	R8, R9			/* R9 = revised count */
dcflush1:			/* primary cache line size is 16 bytes */
	CACHE	PI+HI, 0x00(R8)
	CACHE	PI+HI, 0x10(R8)


@@ 785,8 785,8 @@ dcflush1:			/* primary cache line size is 16 bytes */
	CACHE	PD+HWBI, 0x10(R8)
	CACHE	PD+HWBI, 0x20(R8)
	CACHE	PD+HWBI, 0x30(R8)
	SUB	$0x40, R9
	ADD	$0x40, R8
	SUBU	$0x40, R9
	ADDU	$0x40, R8
	BGTZ	R9, dcflush1
	MOVW	R10, M(STATUS)
	WAIT

M port/alloc.c => port/alloc.c +20 -25
@@ 126,33 126,28 @@ xinit(void)
void*
xspanalloc(ulong size, int align, ulong span)
{
	int i, j;
	ulong a, p, sinc;
	ulong ptr[Spanlist];

	sinc = size/8;
	span = ~(span-1);
	for(i = 0; i < Spanlist; i++) {
		p = (ulong)xalloc(size+align);
		if(p == 0)
			break;
	ulong a, v, t;

	a = (ulong)xalloc(size+align+span);
	if(a == 0)
		panic("xspanalloc: %d %d %lux\n", size, align, span);

	if(span > 2) {
		v = (a + span) & ~(span-1);
		t = v - a;
		if(t > 0)
			xhole(PADDR(a), t);
		t = a + span - v;
		if(t > 0)
			xhole(PADDR(v+size+align), t);
	}
	else
		v = a;

		a = p+align;
		a &= ~(align-1);
		if((a&span) == ((a+size)&span)) {
			for(j = 0; j < i; j++)
				if(ptr[j])
					xfree((void*)ptr[j]);
	if(align > 1)
		v = (v + align) & ~(align-1);

			return (void*)a;
		}
		xfree((void*)p);
		ptr[i] = (ulong)xalloc(sinc);
	}
	USED(sinc);
	xsummary();
	panic("xspanalloc: %d %d %lux\n", size, align, span);	
	return 0;
	return (void*)v;
}

void*