From 26f6aec4c1cb01e685cbdd6e0cd5209ae65a3264 Mon Sep 17 00:00:00 2001
From: David du Colombier <0intro@gmail.com>
Date: Fri, 31 Dec 1993 00:00:00 +0000
Subject: [PATCH] Plan 9 from Bell Labs 1993-12-31

---
 carrera/devether.c |  7 +------
 carrera/l.s        | 16 ++++++++--------
 port/alloc.c       | 45 ++++++++++++++++++++-------------------------
 3 files changed, 29 insertions(+), 39 deletions(-)

diff --git a/carrera/devether.c b/carrera/devether.c
index 59a8430f86cf2fe338af766f6af3dffea0fd2a00..9f6fe34b80c38d27e261fbce82b169cb20349fda 100644
--- a/carrera/devether.c
+++ b/carrera/devether.c
@@ -563,7 +563,7 @@ initbufs(Ether *c)
 	int i;
 	uchar *mem, *base;
 
-	mem = xspanalloc(64*1024, BY2PG, 0);
+	mem = xspanalloc(64*1024, 8, 64*1024);
 	base = mem;
 	mem = CACHELINE(uchar, mem);
 
@@ -581,12 +581,7 @@ initbufs(Ether *c)
 
 	c->cda = UNCACHED(Cam, mem);
 
-	/*
-	 * DMA buffers are cache coherent - but we must not straddle
-	 * a cache line
-	 */
 	mem = CACHELINE(uchar, mem+sizeof(Cam));
-
 	for(i = 0; i < Nrb; i++) {
 		c->rb[i] = UNCACHED(uchar, mem);
 		mem += sizeof(Pbuf)+4;
diff --git a/carrera/l.s b/carrera/l.s
index 5cd8aec2633784936e37fa03f0af81ae6f9633b1..f0be3b55aa1309b4781a5e0a9cee410f8abec7b5 100644
--- a/carrera/l.s
+++ b/carrera/l.s
@@ -742,9 +742,9 @@ TEXT	icflush(SB), $-4			/* icflush(virtaddr, count) */
 	ADDU	R1, R9			/* R9 = last address */
 	MOVW	$(~0x3f), R8
 	AND	R1, R8			/* R8 = first address, rounded down */
-	ADD	$0x3f, R9
+	ADDU	$0x3f, R9
 	AND	$(~0x3f), R9		/* round last address up */
-	SUB	R8, R9			/* R9 = revised count */
+	SUBU	R8, R9			/* R9 = revised count */
 icflush1:			/* primary cache line size is 16 bytes */
 	CACHE	PD+HWB, 0x00(R8)
 	CACHE	PI+HI, 0x00(R8)
@@ -754,8 +754,8 @@ icflush1:			/* primary cache line size is 16 bytes */
 	CACHE	PI+HI, 0x20(R8)
 	CACHE	PD+HWB, 0x30(R8)
 	CACHE	PI+HI, 0x30(R8)
-	SUB	$0x40, R9
-	ADD	$0x40, R8
+	SUBU	$0x40, R9
+	ADDU	$0x40, R8
 	BGTZ	R9, icflush1
 	MOVW	R10, M(STATUS)
 	WAIT
@@ -773,9 +773,9 @@ TEXT	dcflush(SB), $-4			/* dcflush(virtaddr, count) */
 	ADDU	R1, R9			/* R9 = last address */
 	MOVW	$(~0x3f), R8
 	AND	R1, R8			/* R8 = first address, rounded down */
-	ADD	$0x3f, R9
+	ADDU	$0x3f, R9
 	AND	$(~0x3f), R9		/* round last address up */
-	SUB	R8, R9			/* R9 = revised count */
+	SUBU	R8, R9			/* R9 = revised count */
 dcflush1:			/* primary cache line size is 16 bytes */
 	CACHE	PI+HI, 0x00(R8)
 	CACHE	PI+HI, 0x10(R8)
@@ -785,8 +785,8 @@ dcflush1:			/* primary cache line size is 16 bytes */
 	CACHE	PD+HWBI, 0x10(R8)
 	CACHE	PD+HWBI, 0x20(R8)
 	CACHE	PD+HWBI, 0x30(R8)
-	SUB	$0x40, R9
-	ADD	$0x40, R8
+	SUBU	$0x40, R9
+	ADDU	$0x40, R8
 	BGTZ	R9, dcflush1
 	MOVW	R10, M(STATUS)
 	WAIT
diff --git a/port/alloc.c b/port/alloc.c
index 60c8987d295d93a364c3354950eb57c029e2157a..0da2a1a0d312db62fc237af47084499e02892e20 100644
--- a/port/alloc.c
+++ b/port/alloc.c
@@ -126,33 +126,28 @@ xinit(void)
 void*
 xspanalloc(ulong size, int align, ulong span)
 {
-	int i, j;
-	ulong a, p, sinc;
-	ulong ptr[Spanlist];
-
-	sinc = size/8;
-	span = ~(span-1);
-	for(i = 0; i < Spanlist; i++) {
-		p = (ulong)xalloc(size+align);
-		if(p == 0)
-			break;
+	ulong a, v, t;
+
+	a = (ulong)xalloc(size+align+span);
+	if(a == 0)
+		panic("xspanalloc: %d %d %lux\n", size, align, span);
+
+	if(span > 2) {
+		v = (a + span) & ~(span-1);
+		t = v - a;
+		if(t > 0)
+			xhole(PADDR(a), t);
+		t = a + span - v;
+		if(t > 0)
+			xhole(PADDR(v+size+align), t);
+	}
+	else
+		v = a;
 
-		a = p+align;
-		a &= ~(align-1);
-		if((a&span) == ((a+size)&span)) {
-			for(j = 0; j < i; j++)
-				if(ptr[j])
-					xfree((void*)ptr[j]);
+	if(align > 1)
+		v = (v + align) & ~(align-1);
 
-			return (void*)a;
-		}
-		xfree((void*)p);
-		ptr[i] = (ulong)xalloc(sinc);
-	}
-	USED(sinc);
-	xsummary();
-	panic("xspanalloc: %d %d %lux\n", size, align, span);	
-	return 0;
+	return (void*)v;
 }
 
 void*