~kris/9p

9hist

fa5fb28c47d83a12d392eac66f0dc5223e0478f2 — David du Colombier 34 years ago c2f2557
Plan 9 from Bell Labs 1992-04-08
5 files changed, 49 insertions(+), 21 deletions(-)

M pc/devether.c
M pc/kbd.c
M pc/main.c
M pc/trap.c
M port/sturp.c
M pc/devether.c => pc/devether.c +17 -11
@@ 32,6 32,9 @@ enum {
	NPktype		= 9,		/* types/interface */
};

#define NEXT(x, l)	((((x)+1)%(l)) == 0 ? 6: (((x)+1)%(l)))
#define PREV(x, l)	(((x)-1) == 5 ? (l-1): ((x)-1))

/*
 * register offsets from IObase
 */


@@ 389,6 392,7 @@ intr(Ureg *ur)
			outb(cp->iobase+Tcr, 0x20);	/* LB0 */
			outb(cp->iobase+Cr, 0x22);	/* Page0, RD2|STA */
			cp->ovw = 1;
			cp->overflows++;
		}
		/*
		 * we have received packets.


@@ 423,8 427,8 @@ init(Ctlr *cp)
	outb(cp->iobase+Rbcr1, 0);
	outb(cp->iobase+Rcr, 0x04);		/* AB */
	outb(cp->iobase+Tcr, 0x20);		/* LB0 */
	outb(cp->iobase+Bnry, 6);
	cp->bnry = 6;
	outb(cp->iobase+Bnry, cp->bnry);
	cp->ring = (Ring*)(KZERO|RAMbase);
	outb(cp->iobase+Pstart, 6);		/* 6*256 */
	outb(cp->iobase+Pstop, 32);		/* 8*1024/256 */


@@ 434,8 438,8 @@ init(Ctlr *cp)
	outb(cp->iobase+Cr, 0x61);		/* Page1, RD2|STP */
	for(i = 0; i < sizeof(cp->ea); i++)
		outb(cp->iobase+Par0+i, cp->ea[i]);
	outb(cp->iobase+Curr, 6);		/* 6*256 */
	cp->curr = 6;
	cp->curr = cp->bnry+1;
	outb(cp->iobase+Curr, cp->curr);

	outb(cp->iobase+Cr, 0x22);		/* Page0, RD2|STA */
	outb(cp->iobase+Tpsr, 0);


@@ 449,11 453,10 @@ etherreset(void)
	int i;

	cp->iobase = IObase;
	init(cp);
	setvec(Ethervec, intr);

	for(i = 0; i < sizeof(cp->ea); i++)
		cp->ea[i] = inb(cp->iobase+EA+i);
	init(cp);
	setvec(Ethervec, intr);
	memset(cp->ba, 0xFF, sizeof(cp->ba));

	cp->net.name = "ether";


@@ 530,7 533,7 @@ isinput(void *arg)
{
	Ctlr *cp = arg;

	return cp->bnry != cp->curr;
	return NEXT(cp->bnry, 32) != cp->curr;
}

static void


@@ 558,17 561,20 @@ etherkproc(void *arg)
			etherup(cp, (Etherpkt*)bp->rptr, BLEN(bp));
			freeb(bp);
		}

		/*
		 * process any received packets
		 */
		cp->bnry = inb(cp->iobase+Bnry);
		while(cp->bnry != cp->curr){
			rp = &cp->ring[cp->bnry];
		bnry = NEXT(cp->bnry, 32);
		while(bnry != cp->curr){
			rp = &cp->ring[bnry];
			cp->inpackets++;
			etherup(cp, (Etherpkt*)rp->data, ((rp->len1<<8)+rp->len0)-4);
			cp->bnry = rp->next;
			bnry = rp->next;
			cp->bnry = PREV(bnry, 32);
			outb(cp->iobase+Bnry, cp->bnry);
		}

		/*
		 * if we idled input because of overflow,
		 * restart

M pc/kbd.c => pc/kbd.c +8 -3
@@ 188,10 188,7 @@ kbdinit(void)
	int c, s;
	int tries;

	initq(&kbdq);
	setvec(Kbdvec, kbdintr);
	initq(&mouseq);
	setvec(Mousevec, kbdintr);

	/* wait for a quiescent controller */
	while((c = inb(Status)) & (Outbusy | Inready))


@@ 200,6 197,9 @@ kbdinit(void)

	switch(machtype){
	case Attnsx:
		bigcursor();
		setvec(Mousevec, kbdintr);

		/* enable kbd/mouse xfers and interrupts */
		outb(Cmd, 0x60);
		if(outready() < 0)


@@ 220,6 220,11 @@ kbdinit(void)
		if(outready() < 0)
			print("kbd init failed\n");
		outb(Data, 0x65);

		/* set up /dev/eia0 as the mouse */
		uartspecial(0, 0, &mouseq, 1200);
print("uartspecial done\n");
delay(1000);
		break;
	}
}

M pc/main.c => pc/main.c +1 -2
@@ 33,7 33,6 @@ main(void)
	grpinit();
	chaninit();
	alarminit();
	bigcursor();
	chandevreset();
	streaminit();
	swapinit();


@@ 430,8 429,8 @@ exit(void)
		headreset();		/* via headland chip */
		break;
	case At:
		putcr3(0);		/* crash and burn */
		for(;;);
		putcr3(0);		/* crash and burn */
	}
}


M pc/trap.c => pc/trap.c +1 -0
@@ 253,6 253,7 @@ trap(Ureg *ur)
void
dumpregs(Ureg *ur)
{
splhi();
	if(u)
		print("registers for %s %d\n", u->p->text, u->p->pid);
	else

M port/sturp.c => port/sturp.c +22 -5
@@ 120,6 120,7 @@ static void	initoutput(Urp*, int);
static void	initinput(Urp*, int);
static void	urpkproc(void *arg);
static void	urpvomit(char*, Urp*);
static void	tryoutput(Urp*);

Qinfo urpinfo =
{


@@ 316,7 317,7 @@ urpciput(Queue *q, Block *bp)
		DPRINT("rAINIT(c)\n");
		up->state &= ~INITING;
		flushinput(up);
		wakeup(&urpkr);
		tryoutput(up);
		break;

	case INIT0:


@@ 371,6 372,9 @@ urpciput(Queue *q, Block *bp)
 *  Simplifying assumption:  one put == one message && the control byte
 *	is in the first block.  If this isn't true, strange bytes will be
 *	used as control bytes.
 *
 *	There's no input lock.  The channel could be closed while we're
 *	processing a message.
 */
void
urpiput(Queue *q, Block *bp)


@@ 446,7 450,7 @@ urpiput(Queue *q, Block *bp)
		DPRINT("rAINIT\n");
		up->state &= ~INITING;
		flushinput(up);
		wakeup(&urpkr);
		tryoutput(up);
		break;

	case INIT0:


@@ 720,6 724,18 @@ out:
}

/*
 *  try output, this is called by an input process
 */
void
tryoutput(Urp *up)
{
	if(!waserror()){
		output(up);
		poperror();
	}
}

/*
 *  send a control byte, put the byte at the end of the allocated
 *  space in case a lower layer needs header room.
 */


@@ 894,8 910,9 @@ rcvack(Urp *up, int msg)
		break;
	}

	wakeup(&urpkr);
	wakeup(&up->r);
	tryoutput(up);
	if(up->state & CLOSING)
		wakeup(&up->r);
}

/*


@@ 1005,7 1022,7 @@ urpkproc(void *arg)
			qunlock(up);
			poperror();
		}
		tsleep(&urpkr, return0, 0, 1000);
		tsleep(&urpkr, return0, 0, 500);
	}
}