~kris/9p

9hist

f4b25f1bf1b9c485451279a9bb96d026a78e2dbc — David du Colombier 31 years ago 5b3a523
Plan 9 from Bell Labs 1995-03-31
4 files changed, 94 insertions(+), 27 deletions(-)

M pc/devi82365.c
M pc/ether509.c
A pc/ether589.c
M pc/trap.c
M pc/devi82365.c => pc/devi82365.c +6 -12
@@ 246,14 246,8 @@ slotena(Slot *pp)
	/* power up and unreset, wait's are empirical (???) */
	wrreg(pp, Rpc, Fautopower|Foutena|Fcardena);
	delay(300);
	wrreg(pp, Rigc, Fnotreset);
	delay(500);

	wrreg(pp, Rpc, 0);
	delay(500);

	wrreg(pp, Rpc, Fautopower|Foutena|Fcardena);
	delay(300);
	wrreg(pp, Rigc, 0);
	delay(100);
	wrreg(pp, Rigc, Fnotreset);
	delay(500);



@@ 263,7 257,7 @@ slotena(Slot *pp)
		cisread(pp);
		pp->enabled = 1;
	} else
		wrreg(pp, Rpc, 0);
		wrreg(pp, Rpc, Fautopower);
}

/*


@@ 272,8 266,8 @@ slotena(Slot *pp)
static void
slotdis(Slot *pp)
{
	wrreg(pp, Rwe, 0);		/* no windows */
	wrreg(pp, Rpc, 0);		/* turn off card power */
	wrreg(pp, Rpc, 0);	/* turn off card power */
	wrreg(pp, Rwe, 0);	/* no windows */
	pp->enabled = 0;
}



@@ 1306,7 1300,7 @@ tentry(Slot *pp, int ttype)
	case 3:
		if(readc(pp, &c) != 1)
			return;
		for(i = 0; i <= c&0x7; i++)
		for(i = 0; i <= (c&0x7); i++)
			memspace(pp, (c>>5)&0x3, (c>>3)&0x3, c&0x80);
		break;
	}

M pc/ether509.c => pc/ether509.c +7 -14
@@ 279,7 279,6 @@ interrupt(Ureg *ur, void *arg)
	Ether *ether;

	USED(ur);

	ether = arg;
	port = ether->port;



@@ 552,18 551,11 @@ tcm579(Ether *ether)
	return 0;
}

static ulong
tcm589(Ether *ether)
{
	USED(ether);
	return 0;
}

/*
 * Get configuration parameters.
 */
static int
reset(Ether *ether)
int
ether509reset(Ether *ether)
{
	int i, eax;
	uchar ea[Eaddrlen];


@@ 588,13 580,13 @@ reset(Ether *ether)
			break;
		}
	}
	if(strcmp(ether->type, "3C589") == 0)
		port = ether->port;
	if(port == 0)
		port = tcm579(ether);
	if(port == 0)
		port = tcm509(ether);
	if(port == 0)
		port = tcm589(ether);
	if(port == 0)
		return -1;

	/*


@@ 603,7 595,8 @@ reset(Ether *ether)
	 * The EEPROM command is 8 bits, the lower 6 bits being
	 * the address offset.
	 */
	ether->irq = (ins(port+ResourceConfig)>>12) & 0x0F;
	if(strcmp(ether->type, "3C589") != 0)
		ether->irq = (ins(port+ResourceConfig)>>12) & 0x0F;
	for(eax = 0, i = 0; i < 3; i++, eax += 2){
		while(ins(port+EEPROMcmd) & 0x8000)
			;


@@ 680,5 673,5 @@ reset(Ether *ether)
void
ether509link(void)
{
	addethercard("3C509",  reset);
	addethercard("3C509",  ether509reset);
}

A pc/ether589.c => pc/ether589.c +80 -0
@@ 0,0 1,80 @@
#include "u.h"
#include "../port/lib.h"
#include "mem.h"
#include "dat.h"
#include "fns.h"
#include "io.h"
#include "../port/error.h"
#include "../port/netif.h"

#include "etherif.h"

enum {
	SelectWindow	= 0x01,		/* SelectWindow command */

	Command		= 0x0E,		/* all windows */
	Status		= 0x0E,

	ManufacturerID	= 0x00,		/* window 0 */
	ProductID	= 0x02,
	ConfigControl	= 0x04,
	AddressConfig	= 0x06,
	ResourceConfig	= 0x08,
	EEPROMcmd	= 0x0A,
	EEPROMdata	= 0x0C,
};

#define COMMAND(port, cmd, a)	outs(port+Command, ((cmd)<<11)|(a))

extern int ether509reset(Ether*);

static int
reset(Ether *ether)
{
	int slot;
	int port;
	ushort x;

	if(ether->irq == 0)
		ether->irq = 10;
	if(ether->port == 0)
		ether->port = 0x3F0;
	port = ether->port;

	slot = pcmspecial("3C589", ether);
	if(slot < 0)
		return -1;

	/* set Window 0 configuration registers */
	COMMAND(port, SelectWindow, 0);

	/* ROM size & base - must be set before we can access ROM */
	/* transceiver type (for now always 10baseT) */
	x = ins(port + AddressConfig);
	outs(port + AddressConfig, x & 0x20);

	/* IRQ must be 3 on 3C589 */
	x = ins(port + ResourceConfig);
	outs(port + ResourceConfig, 0x3000 | (x&0xfff));

	/* move product ID to register */
	while(ins(port+EEPROMcmd) & 0x8000)
		;
	outs(port+EEPROMcmd, (2<<6)|3);
	while(ins(port+EEPROMcmd) & 0x8000)
		;
	x = ins(port+EEPROMdata);
	outs(port + ProductID, x);

	if(ether509reset(ether) < 0){
		pcmspecialclose(slot);
		return -1;
	}
	return 0;
}

void
ether589link(void)
{
	addethercard("3C589", reset);
}

M pc/trap.c => pc/trap.c +1 -1
@@ 199,7 199,7 @@ trapinit(void)
	/*
	 *  Set up the second 8259 interrupt processor.
	 *  Make 8259 interrupts start at CPU vector Int1vec.
	 *  Set the 8259 as master with edge triggered
	 *  Set the 8259 as master with level triggered
	 *  input with fully nested interrupts.
	 */
	outb(Int1ctl, (1<<4)|(1<<3)|(1<<0));	/* ICW1 - master, level triggered,