~kris/9p

9hist

ef1d1140da4a0f49c8263d70f33392cd46e17bd1 — David du Colombier 29 years ago 9948aa3
Plan 9 from Bell Labs 1997-08-06
10 files changed, 42 insertions(+), 41 deletions(-)

M ip/devip.c
M ip/il.c
M ip/ip.c
M ip/ip.h
M ip/netlog.c
M ip/tcp.c
M ip/udp.c
M pc/ether82557.c
M pc/etherelnk3.c
M port/qio.c
M ip/devip.c => ip/devip.c +2 -2
@@ 918,9 918,9 @@ Fspcolstats(char *buf, int len)
	n = 0;
	for(p = fs.p; *p; p++)
		n += snprint(buf + n, len - n,
			"%s: csum %d hlen %d len %d order %d rexmit %d\n",
			"%s: csum %d hlen %d len %d order %d rexmit %d wc %d\n",
			(*p)->name, (*p)->csumerr, (*p)->hlenerr, (*p)->lenerr,
			(*p)->order, (*p)->rexmit);
			(*p)->order, (*p)->rexmit, (*p)->wclosed);
	return n;
}


M ip/il.c => ip/il.c +2 -2
@@ 128,7 128,7 @@ enum
	Seconds		= 1000,
	Iltickms 	= 100,		/* time base */

	Ackkeepalive	= 6000*Iltickms,
	Ackkeepalive	= 600*Seconds,
	Acktime		= 2*Iltickms,	/* max time twixt message rcvd & ack sent */

	Slowtime 	= 90*Seconds,	/* max time waiting for an ack before hangup */


@@ 1015,7 1015,7 @@ loop:
void
ilbackoff(Ilcb *ic)
{
	ic->fasttime += ic->fasttime<<1;
	ic->fasttime += ic->fasttime>>1;
}

char*

M ip/ip.c => ip/ip.c +4 -2
@@ 224,6 224,8 @@ initfrag(int size)

void (*ipextprotoiput)(Block*);

//#define DBG(x)	if((logmask & Logipmsg) && (iponly == 0 || x == iponly))netlog

void
ipiput(Media *m, Block *bp)
{


@@ 232,8 234,8 @@ ipiput(Media *m, Block *bp)
	ushort frag;
	int notforme;

/*	h = (Iphdr *)(bp->rp);
	netlog(Logip, "ipiput %I %I len %d proto %d\n", h->src, h->dst, BLEN(bp), h->proto);*/
//	h = (Iphdr *)(bp->rp);
//	DBG(nhgetl(h->src))(Logipmsg, "ipiput %I %I len %d proto %d\n", h->src, h->dst, BLEN(bp), h->proto);

	/* Ensure we have enough data to process */
	if(BLEN(bp) < IPHDR) {

M ip/ip.h => ip/ip.h +3 -0
@@ 183,6 183,7 @@ struct Proto
	ulong		lenerr;			/* short packet */
	ulong		order;			/* out of order */
	ulong		rexmit;			/* retransmissions */
	ulong		wclosed;		/* window closed */
};

struct Fs


@@ 218,6 219,8 @@ enum
	Logppp=		1<<10,
	Logtcpmsg=	1<<11,
	Logigmp=	1<<12,
	Logudpmsg=	1<<13,
	Logipmsg=	1<<14,
};

extern int	logmask;	/* mask of things to debug */

M ip/netlog.c => ip/netlog.c +2 -0
@@ 46,6 46,8 @@ static Logflag flags[] =
	{ "ilmsg",	Logil|Logilmsg, },
	{ "gre",	Loggre, },
	{ "tcpmsg",	Logtcp|Logtcpmsg, },
	{ "udpmsg",	Logudp|Logudpmsg, },
	{ "ipmsg",	Logip|Logipmsg, },
	{ nil,		0, },
};


M ip/tcp.c => ip/tcp.c +1 -0
@@ 1469,6 1469,7 @@ tcpoutput(Conv *s)
		 * window probes to one
		 */
		if(tcb->snd.wnd == 0){
			tcp.wclosed++;
			if(sent != 0) {
				if ((tcb->flags&FORCE) == 0)
					break;

M ip/udp.c => ip/udp.c +6 -14
@@ 95,8 95,8 @@ udpannounce(Conv *c, char** argv, int argc)
static void
udpcreate(Conv *c)
{
	c->rq = qopen(16*1024, 1, 0, 0);
	c->wq = qopen(16*1024, 0, 0, 0);
	c->rq = qopen(64*1024, 1, 0, 0);
	c->wq = qopen(64*1024, 0, 0, 0);
}

static void


@@ 124,7 124,7 @@ udpkick(Conv *c, int l)
	Udphdr *uh;
	ushort rport;
	Ipaddr laddr, raddr;
	Block *bp, *f;
	Block *bp;
	Udpcb *ucb;
	int dlen, ptcllen;



@@ 158,18 158,7 @@ udpkick(Conv *c, int l)
		laddr = 0;
	}

	/* Round packet up to even number of bytes */
	dlen = blocklen(bp);
	if(dlen & 1) {
		for(f = bp; f->next; f = f->next)
			;
		if(f->wp >= f->lim) {
			f->next = allocb(1);
			f = f->next;
		}
		*f->wp++ = 0;
		dlen++;	
	}

	/* Make space to fit udp & ip header */
	bp = padblock(bp, UDP_IPHDR+UDP_HDRSIZE);


@@ 267,6 256,9 @@ udpiput(Media *m, Block *bp)
		return;
	}

	netlog(Logudpmsg, "udp: %I.%d -> %I.%d l %d\n", uh->udpsrc, rport,
		uh->udpdst, lport, len);

	ucb = (Udpcb*)c->ptcl;

	if(ucb->headers) {

M pc/ether82557.c => pc/ether82557.c +20 -20
@@ 1,10 1,11 @@
/*
 * Intel 82557 Fast Ethernet PCI Bus LAN Controller
 * as found on the Intel EtherExpress PRO/100B. This chip is full
 * of smarts, unfortunately none of them are in the right place.
 * of smarts, unfortunately they're not all in the right place.
 * To do:
 *	the PCI scanning code could be made common to other adapters;
 *	auto-negotiation;
 *	full-duplex;
 *	optionally use memory-mapped registers.
 */
#include "u.h"


@@ 27,7 28,7 @@ enum {
enum {					/* CSR */
	Status		= 0x00,		/* byte or word (word includes Ack) */
	Ack		= 0x01,		/* byte */
	Command		= 0x02,		/* byte or word (word includes Interrupt) */
	CommandR	= 0x02,		/* byte or word (word includes Interrupt) */
	Interrupt	= 0x03,		/* byte */
	General		= 0x04,		/* dword */
	Port		= 0x08,		/* dword */


@@ 298,10 299,10 @@ custart(Ctlr* ctlr)
	ctlr->cbqbusy = 1;

	ilock(&ctlr->rlock);
	while(csr8r(ctlr, Command))
	while(csr8r(ctlr, CommandR))
		;
	csr32w(ctlr, General, PADDR(&ctlr->cbqhead->command));
	csr8w(ctlr, Command, CUstart);
	csr8w(ctlr, CommandR, CUstart);
	iunlock(&ctlr->rlock);
}



@@ 338,10 339,10 @@ attach(Ether* ether)
	ilock(&ctlr->rlock);
	status = csr16r(ctlr, Status);
	if((status & RUstatus) == RUidle){
		while(csr8r(ctlr, Command))
		while(csr8r(ctlr, CommandR))
			;
		csr32w(ctlr, General, PADDR(ctlr->rfdhead->rp));
		csr8w(ctlr, Command, RUstart);
		csr8w(ctlr, CommandR, RUstart);
	}
	iunlock(&ctlr->rlock);
}


@@ 378,9 379,9 @@ ifstat(Ether* ether, void* a, long n, ulong offset)
	ctlr->dump[16] = 0;

	ilock(&ctlr->rlock);
	while(csr8r(ctlr, Command))
	while(csr8r(ctlr, CommandR))
		;
	csr8w(ctlr, Command, DumpSC);
	csr8w(ctlr, CommandR, DumpSC);
	iunlock(&ctlr->rlock);

	/*


@@ 535,9 536,9 @@ interrupt(Ureg*, void* arg)

		if(status & StatRNR){
			lock(&ctlr->rlock);
			while(csr8r(ctlr, Command))
			while(csr8r(ctlr, CommandR))
				;
			csr8w(ctlr, Command, RUresume);
			csr8w(ctlr, CommandR, RUresume);
			unlock(&ctlr->rlock);

			status &= ~StatRNR;


@@ 726,9 727,8 @@ reset(Ether* ether)
	}

	/*
	 * Any adapter matches if no ether->port is supplied, otherwise the
	 * ports must match. First see if an adapter that fits the bill has
	 * already been found. If not, scan for another.
	 * Any adapter matches if no port is supplied,
	 * otherwise the ports must match.
	 */
	port = 0;
	bpp = &adapter;


@@ 763,19 763,19 @@ reset(Ether* ether)
	csr32w(ctlr, Port, 0);
	delay(1);

	while(csr8r(ctlr, Command))
	while(csr8r(ctlr, CommandR))
		;
	csr32w(ctlr, General, 0);
	csr8w(ctlr, Command, LoadRUB);
	csr8w(ctlr, CommandR, LoadRUB);

	while(csr8r(ctlr, Command))
	while(csr8r(ctlr, CommandR))
		;
	csr8w(ctlr, Command, LoadCUB);
	csr8w(ctlr, CommandR, LoadCUB);

	while(csr8r(ctlr, Command))
	while(csr8r(ctlr, CommandR))
		;
	csr32w(ctlr, General, PADDR(ctlr->dump));
	csr8w(ctlr, Command, LoadDCA);
	csr8w(ctlr, CommandR, LoadDCA);
	iunlock(&ctlr->rlock);

	/*


@@ 827,7 827,7 @@ reset(Ether* ether)
	 * the station address with the Individual Address Setup command.
	 */
	memset(ea, 0, Eaddrlen);
	if(!memcmp(ea, ether->ea, Eaddrlen)){
	if(memcmp(ea, ether->ea, Eaddrlen) == 0){
		for(i = 0; i < Eaddrlen/2; i++){
			x = hy93c46r(ctlr, i);
			ether->ea[2*i] = x;

M pc/etherelnk3.c => pc/etherelnk3.c +1 -1
@@ 6,7 6,7 @@
 *	autoSelect;
 *	PCI latency timer and master enable;
 *	errata list;
 *	3C90x full busmastering;
 *	limit 3C90x transmit queue;
 *	rewrite all initialisation.
 *
 * Product ID:

M port/qio.c => port/qio.c +1 -0
@@ 1043,6 1043,7 @@ qclose(Queue *q)
	/* mark it */
	ilock(q);
	q->state |= Qclosed;
	q->state &= ~(Qflow|Qstarve);
	strcpy(q->err, Ehungup);
	bfirst = q->bfirst;
	q->bfirst = 0;