37 files changed, 7998 insertions(+), 34 deletions(-)

A alphapc/arch164.c
A alphapc/axp.h
A alphapc/cga.c
A alphapc/clock.c
A alphapc/dat.h
A alphapc/devether.c
A alphapc/devfloppy.c
A alphapc/devvga.c
A alphapc/dma.c
A alphapc/etherif.h
A alphapc/faultalpha.c
A alphapc/floppy.h
A alphapc/fns.h
A alphapc/fptrap.c
A alphapc/i8259.c
A alphapc/io.h
A alphapc/kbd.c
A alphapc/l.s
A alphapc/main.c
A alphapc/mem.h
A alphapc/mmu.c
A alphapc/mouse.c
A alphapc/ns16552.h
A alphapc/pci.c
A alphapc/screen.c
A alphapc/screen.h
A alphapc/segment.h
A alphapc/trap.c
A alphapc/vga.c
A alphapc/vgargb524.c
A alphapc/vgas3.c
A alphapc/vgax.c
M mpc/clock.c
M mpc/devuart.c
M mpc/main.c
M mpc/mem.h
M port/devssl.c

@@ 0,0 1,389 @@
+/*
+ *	EB164 and similar
+ *	CPU:	21164
+ *	Core Logic: 21172 CIA or 21174 PYXIS
+  */
+#include	"u.h"
+#include	"../port/lib.h"
+#include	"mem.h"
+#include	"dat.h"
+#include	"fns.h"
+#include	"io.h"
+#include	"ureg.h"
+
+static ulong *core;
+static ulong *wind;
+
+static ulong windsave[16];
+static ulong coresave[1];
+
+ulong	iobase0;
+ulong	iobase1;
+#define	iobase(p)	(iobase0+(p))
+
+static int
+ident(void)
+{
+	return 0;	/* bug! */
+}
+
+static void *
+kmapio(ulong space, ulong offset, int size)
+{
+	return kmapv(((uvlong)space<<32LL)|offset, size);
+}
+
+static void
+coreinit(void)
+{
+	int i;
+
+	core = kmapio(0x87, 0x40000000, 0x10000);
+	wind = kmapio(0x87, 0x60000000, 0x1000);
+
+	iobase0 = (ulong)kmapio(0x89, 0, 0x20000);
+
+	/* hae_io = core[0x440/4];
+	iobase1 = (ulong)kmapio(0x89, hae_io, 0x10000); */
+
+	/* save critical parts of hardware memory mapping */
+	for (i = 4; i < 8; i++) {
+		windsave[4*(i-4)+0] = wind[(i*0x100+0x00)/4];
+		windsave[4*(i-4)+1] = wind[(i*0x100+0x40)/4];
+		windsave[4*(i-4)+2] = wind[(i*0x100+0x80)/4];
+	}
+	coresave[0] = core[0x140/4];
+
+	/* direct map bottom 2G PCI target space to KZERO in window 1 */
+	wind[0x500/4] = KZERO|1;
+	wind[0x540/4] = 0x7ff00000;
+	wind[0x580/4] = 0;
+
+	/* disable other windows */
+	wind[0x400/4] = 0;
+	wind[0x600/4] = 0;
+	wind[0x700/4] = 0;
+
+	/* clear error state */
+	core[0x8200/4] = 0x7ff;
+
+	/* set config: byte/word enable, no monster window, etc. */
+	core[0x140/4] = 1;
+
+	/* turn off mcheck on master abort.  now we can probe PCI space. */
+	core[0x8280/4] &= ~(1<<7);
+
+	/* set up interrupts. */
+	i8259init();
+	cserve(52, 4);		/* enable SIO interrupt */
+}
+
+static void
+corehello(void)
+{
+	print("cpu%d: CIA revision %d; cnfg %lux cntrl %lux\n",
+			0,	/* BUG */
+			core[0x80/4] & 0x7f, core[0x140/4], core[0x100/4]);
+	print("cpu%d: HAE_IO %lux\n", 0, core[0x440/4]);
+	print("\n");
+}
+
+static void
+coredetach(void)
+{
+	int i;
+
+	for (i = 4; i < 8; i++) {
+		wind[(i*0x100+0x00)/4] = windsave[4*(i-4)+0];
+		wind[(i*0x100+0x40)/4] = windsave[4*(i-4)+1];
+		wind[(i*0x100+0x80)/4] = windsave[4*(i-4)+2];
+	}
+	core[0x140/4] = coresave[0];
+/*	for (i = 0; i < 4; i++)
+		if (i != 4)
+			cserve(53, i);		/* disable interrupts */
+}
+
+static Lock	pcicfgl;
+static ulong	pcimap[256];
+
+static void*
+pcicfg2117x(int tbdf, int rno)
+{
+	int space, bus;
+	ulong base;
+
+	bus = BUSBNO(tbdf);
+	lock(&pcicfgl);
+	base = pcimap[bus];
+	if (base == 0) {
+		if(bus)
+			space = 0x8B;
+		else
+			space = 0x8A;
+		pcimap[bus] = base = (ulong)kmapio(space, MKBUS(0, bus, 0, 0), (1<<16));
+	}
+	unlock(&pcicfgl);
+	return (void*)(base + BUSDF(tbdf) + rno);
+}
+
+static void*
+pcimem2117x(int addr, int len)
+{
+	return kmapio(0x88, addr, len);
+}
+
+/*
+ *	interrupts -- adapted from PC, needs work.
+ */
+
+static Lock irqctllock;
+static Irqctl *irqctl[256];
+static char irqmask[3];
+
+static void
+intr164(Ureg *ur)
+{
+	int i, v;
+	Irqctl *ctl;
+	Irq *irq;
+	Mach *mach;
+
+	v = (ulong)ur->a1>>4;
+	if (v < 0x80) {
+		iprint("unknown device intr v %d\n", v);
+		return;
+	}
+	v -= 0x80;
+	if(v < 256 && (ctl = irqctl[v])){
+		if(ctl->isintr){
+			m->intr++;
+			if(ctl->isr)
+				ctl->isr(v);
+/*				if(v >= VectorPIC && v <= MaxVectorPIC)
+				m->lastintr = v-VectorPIC; */
+		}
+
+		for(irq = ctl->irq; irq; irq = irq->next)
+			irq->f(ur, irq->a);
+
+		if(ctl->eoi)
+			ctl->eoi(v);
+	}
+	else if(v >= VectorPIC && v <= MaxVectorPIC){
+		/*
+		 * An unknown interrupt.
+		 * Check for a default IRQ7. This can happen when
+		 * the IRQ input goes away before the acknowledge.
+		 * In this case, a 'default IRQ7' is generated, but
+		 * the corresponding bit in the ISR isn't set.
+		 * In fact, just ignore all such interrupts.
+		 */
+		iprint("cpu%d: spurious interrupt %d, last %d",
+			m->machno, v-VectorPIC, 0 /*m->lastintr*/);
+		for(i = 0; i < 32; i++){
+			if(!(active.machs & (1<<i)))
+				continue;
+			mach = MACHP(i);
+			if(m->machno == mach->machno)
+				continue;
+			iprint(": cpu%d: last %d", mach->machno, 0 /*mach->lastintr*/);
+		}
+		iprint("\n");
+/*			m->spuriousintr++; */
+		return;
+	}
+	else{
+		dumpregs(ur);
+		panic("unknown intr: %d\n", v); /* */
+	}
+}
+
+static int
+intrenable164(int v, void (*f)(Ureg*, void*), void*a, int tbdf)
+{
+	Irq * irq;
+	Irqctl *ctl;
+
+	lock(&irqctllock);
+	if(irqctl[v] == 0){
+		ctl = xalloc(sizeof(Irqctl));
+/* this is all wrong; FIXME! */
+		if(BUSTYPE(tbdf) == BusPCI)
+			cserve(52, v-VectorPCI);
+		else if(v >= VectorPIC && i8259enable(v, tbdf, ctl) == -1){
+			unlock(&irqctllock);
+			iprint("intrenable: didn't find v %d, tbdf 0x%uX\n", v, tbdf);
+			xfree(ctl);
+			return -1;
+		}
+		irqctl[v] = ctl;
+	}
+	ctl = irqctl[v];
+	irq = xalloc(sizeof(Irq));
+	irq->f = f;
+	irq->a = a;
+	irq->next = ctl->irq;
+	ctl->irq = irq;
+	unlock(&irqctllock);
+	return 0;
+}
+
+/*
+ *	I have a function pointer in PCArch for every one of these, because on
+ *	some Alphas we have to use sparse mode, but on others we can use
+ *	MOVB et al.  Additionally, the PC164 documentation threatened us
+ *	with the lie that the SIO is in region B, but everything else in region A.
+ *	This turned out not to be the case.  Given the cost of this solution, it
+ *	may be better just to use sparse mode for I/O space on all platforms.
+ */
+int
+inb2117x(int port)
+{
+	mb();
+	return *(uchar*)(iobase(port));
+}
+
+ushort
+ins2117x(int port)
+{
+	mb();
+	return *(ushort*)(iobase(port));
+}
+
+ulong
+inl2117x(int port)
+{
+	mb();
+	return *(ulong*)(iobase(port));
+}
+
+void
+outb2117x(int port, int val)
+{
+	mb();
+	*(uchar*)(iobase(port)) = val;
+}
+
+void
+outs2117x(int port, ushort val)
+{
+	mb();
+	*(ushort*)(iobase(port)) = val;
+}
+
+void
+outl2117x(int port, ulong val)
+{
+	mb();
+	*(ulong*)(iobase(port)) = val;
+}
+
+void
+insb2117x(int port, void *buf, int len)
+{
+	int i;
+	uchar *p, *q;
+
+	p = (uchar*)iobase(port);
+	q = buf;
+	for(i = 0; i < len; i++){
+		mb();
+		*q++ = *p;
+	}
+}
+
+void
+inss2117x(int port, void *buf, int len)
+{
+	int i;
+	ushort *p, *q;
+
+	p = (ushort*)iobase(port);
+	q = buf;
+	for(i = 0; i < len; i++){
+		mb();
+		*q++ = *p;
+	}
+}
+
+void
+insl2117x(int port, void *buf, int len)
+{
+	int i;
+	ulong *p, *q;
+
+	p = (ulong*)iobase(port);
+	q = buf;
+	for(i = 0; i < len; i++){
+		mb();
+		*q++ = *p;
+	}
+}
+
+void
+outsb2117x(int port, void *buf, int len)
+{
+	int i;
+	uchar *p, *q;
+
+	p = (uchar*)iobase(port);
+	q = buf;
+	for(i = 0; i < len; i++){
+		mb();
+		*p = *q++;
+	}
+}
+
+void
+outss2117x(int port, void *buf, int len)
+{
+	int i;
+	ushort *p, *q;
+
+	p = (ushort*)iobase(port);
+	q = buf;
+	for(i = 0; i < len; i++){
+		mb();
+		*p = *q++;
+	}
+}
+
+void
+outsl2117x(int port, void *buf, int len)
+{
+	int i;
+	ulong *p, *q;
+
+	p = (ulong*)iobase(port);
+	q = buf;
+	for(i = 0; i < len; i++){
+		mb();
+		*p = *q++;
+	}
+}
+
+PCArch arch164 = {
+	"EB164",
+	ident,
+	coreinit,
+	corehello,
+	coredetach,
+	pcicfg2117x,
+	pcimem2117x,
+	intr164,
+	intrenable164,
+
+	inb2117x,
+	ins2117x,
+	inl2117x,
+	outb2117x,
+	outs2117x,
+	outl2117x,
+	insb2117x,
+	inss2117x,
+	insl2117x,
+	outsb2117x,
+	outss2117x,
+	outsl2117x,
+};

@@ 0,0 1,71 @@
+typedef struct Hwrpb	Hwrpb;
+typedef struct Hwcpu	Hwcpu;
+typedef struct Hwdsr	Hwdsr;
+
+struct Hwrpb
+{
+	uvlong	phys;
+	uvlong	sign;
+	uvlong	rev;
+	uvlong	size;
+	uvlong	cpu0;
+	uvlong	by2pg;
+	uvlong	pabits;
+	uvlong	maxasn;
+	char		ssn[16];
+	uvlong	systype;
+	uvlong	sysvar;
+	uvlong	sysrev;
+	uvlong	ifreq;
+	uvlong	cfreq;
+	uvlong	vptb;
+	uvlong	resv;
+	uvlong	tbhint;
+	uvlong	ncpu;
+	uvlong	cpulen;
+	uvlong	cpuoff;
+	uvlong	nctb;
+	uvlong	ctblen;
+	uvlong	ctboff;
+	uvlong	ccrboff;
+	uvlong	memoff;
+	uvlong	confoff;
+	uvlong	fruoff;
+	uvlong	termsaveva;
+	uvlong	termsavex;
+	uvlong	termrestva;
+	uvlong	termrestx;
+	uvlong	termresetva;
+	uvlong	termresetx;
+	uvlong	sysresv;
+	uvlong	hardresv;
+	uvlong	csum;
+	uvlong	rxrdymsk;
+	uvlong	txrdymsk;
+	uvlong	dsroff;		/* rev 6 or higher */
+};
+
+extern Hwrpb* hwrpb;
+
+struct Hwcpu
+{
+	uvlong	hwpcb[16];
+	uvlong	state;
+	uvlong	palmainlen;
+	uvlong	palscratchlen;
+	uvlong	palmainpa;
+	uvlong	palscratchpa;
+	uvlong	palrev;
+	uvlong	cputype;
+	uvlong	cpuvar;
+	uvlong	cpurev;
+	uvlong	serial[2];
+	/* more crap ... */
+};
+
+struct Hwdsr
+{
+	vlong	smm;
+	uvlong	lurtoff;
+	uvlong	sysnameoff;
+};

@@ 0,0 1,113 @@
+#include "u.h"
+#include "../port/lib.h"
+#include "mem.h"
+#include "dat.h"
+#include "fns.h"
+#include "../port/error.h"
+#include "io.h"
+
+enum {
+	Width		= 160,
+	Height		= 25,
+
+	Attr		= 0x4f,	/* white on blue */
+};
+
+static ulong	cgabase;
+#define CGASCREENBASE	((uchar*)cgabase)
+
+static int cgapos;
+static int screeninitdone;
+static Lock cgascreenlock;
+
+static uchar
+cgaregr(int index)
+{
+	outb(0x3D4, index);
+	return inb(0x3D4+1) & 0xFF;
+}
+
+static void
+cgaregw(int index, int data)
+{
+	outb(0x3D4, index);
+	outb(0x3D4+1, data);
+}
+
+static void
+movecursor(void)
+{
+	cgaregw(0x0E, (cgapos/2>>8) & 0xFF);
+	cgaregw(0x0F, cgapos/2 & 0xFF);
+	CGASCREENBASE[cgapos+1] = Attr;
+}
+
+static void
+cgascreenputc(int c)
+{
+	int i;
+
+	if(c == '\n'){
+		cgapos = cgapos/Width;
+		cgapos = (cgapos+1)*Width;
+	}
+	else if(c == '\t'){
+		i = 8 - ((cgapos/2)&7);
+		while(i-->0)
+			cgascreenputc(' ');
+	}
+	else if(c == '\b'){
+		if(cgapos >= 2)
+			cgapos -= 2;
+		cgascreenputc(' ');
+		cgapos -= 2;
+	}
+	else{
+		CGASCREENBASE[cgapos++] = c;
+		CGASCREENBASE[cgapos++] = Attr;
+	}
+	if(cgapos >= Width*Height){
+		memmove(CGASCREENBASE, &CGASCREENBASE[Width], Width*(Height-1));
+		for (i = Width*(Height-1); i < Width*Height;) {
+			CGASCREENBASE[i++] = 0x20;
+			CGASCREENBASE[i++] = Attr;
+		}
+		cgapos = Width*(Height-1);
+	}
+	movecursor();
+}
+
+void
+screeninit(void)
+{
+	cgabase = (ulong)arch->pcimem(0xB8000, 0x8000);
+
+	cgapos = cgaregr(0x0E)<<8;
+	cgapos |= cgaregr(0x0F);
+	cgapos *= 2;
+	screeninitdone = 1;
+}
+
+static void
+cgascreenputs(char* s, int n)
+{
+	if(!screeninitdone)
+		return;
+	if(!islo()){
+		/*
+		 * Don't deadlock trying to
+		 * print in an interrupt.
+		 */
+		if(!canlock(&cgascreenlock))
+			return;
+	}
+	else
+		lock(&cgascreenlock);
+
+	while(n-- > 0)
+		cgascreenputc(*s++);
+
+	unlock(&cgascreenlock);
+}
+
+void (*screenputs)(char*, int) = cgascreenputs;

@@ 0,0 1,146 @@
+#include	"u.h"
+#include	"../port/lib.h"
+#include	"mem.h"
+#include	"dat.h"
+#include	"fns.h"
+#include	"io.h"
+
+#include	"ureg.h"
+
+void (*kproftimer)(ulong);
+
+typedef struct Clock0link Clock0link;
+typedef struct Clock0link {
+	void		(*clock)(void);
+	Clock0link*	link;
+} Clock0link;
+
+static Clock0link *clock0link;
+static Lock clock0lock;
+
+void
+addclock0link(void (*clock)(void))
+{
+	Clock0link *lp;
+
+	if((lp = malloc(sizeof(Clock0link))) == 0){
+		print("addclock0link: too many links\n");
+		return;
+	}
+	ilock(&clock0lock);
+	lp->clock = clock;
+	lp->link = clock0link;
+	clock0link = lp;
+	iunlock(&clock0lock);
+}
+
+
+/*
+ *  delay for l milliseconds more or less.  delayloop is set by
+ *  clockinit() to match the actual CPU speed.
+ */
+void
+delay(int l)
+{
+	ulong i, j;
+
+	j = m->delayloop;
+	while(l-- > 0)
+		for(i=0; i < j; i++)
+			;
+}
+
+void
+microdelay(int l)
+{
+	ulong i, j;
+
+//	j = m->delayloop/1000;
+j = 10000;
+	while(l-- > 0)
+		for(i=0; i < j; i++)
+			;
+}
+
+void
+clockinit(void)
+{
+m->delayloop = 250*1000;	/* BUG */
+#ifdef	NOTYET
+	long x;
+
+	m->delayloop = m->speed*100;
+	do {
+		x = rdcount();
+		delay(10);
+		x = rdcount() - x;
+	} while(x < 0);
+
+	/*
+	 *  fix count
+	 */
+	m->delayloop = (m->delayloop*m->speed*1000*10)/x;
+	if(m->delayloop == 0)
+		m->delayloop = 1;
+
+/*	wrcompare(rdcount()+(m->speed*1000000)/HZ); */
+#endif
+}
+
+void
+clock(Ureg *ur)
+{
+	Clock0link *lp;
+	static int count;
+
+	/* HZ == 100, timer == 1024Hz.  error < 1ms */
+	count += 100;
+	if (count < 1024)
+		return;
+	count -= 1024;
+
+	m->ticks++;
+	if(m->proc)
+		m->proc->pc = ur->pc;
+
+	accounttime();
+
+	if(kproftimer != nil)
+		kproftimer(ur->pc);
+
+	if((active.machs&(1<<m->machno)) == 0)
+		return;
+
+	if(active.exiting && (active.machs & (1<<m->machno))) {
+		print("someone's exiting\n");
+		exit(0);
+	}
+
+	checkalarms();
+	if(m->machno == 0){
+		lock(&clock0lock);
+		for(lp = clock0link; lp; lp = lp->link)
+			lp->clock();
+		unlock(&clock0lock);
+	}
+
+	if(up == 0 || up->state != Running)
+		return;
+
+	if(anyready())
+		sched();
+
+	/* user profiling clock */
+	if(ur->status & UMODE) {
+		(*(ulong*)(USTKTOP-BY2WD)) += TK2MS(1);
+		segclock(ur->pc);
+	}
+}
+
+vlong
+fastticks(uvlong *hz)
+{
+	if (hz)
+		*hz = 100;
+	return m->ticks;
+}

@@ 0,0 1,228 @@
+typedef struct Conf	Conf;
+typedef struct FPsave	FPsave;
+typedef struct Irq	Irq;
+typedef struct Irqctl	Irqctl;
+typedef struct ISAConf	ISAConf;
+typedef struct Label	Label;
+typedef struct Lock	Lock;
+typedef struct Mach	Mach;
+typedef struct Notsave	Notsave;
+typedef struct Page	Page;
+typedef struct PCArch	PCArch;
+typedef struct PCB	PCB;
+typedef struct Pcidev	Pcidev;
+typedef struct PMMU	PMMU;
+typedef struct Sys	Sys;
+typedef struct Ureg	Ureg;
+typedef struct Proc	Proc;
+
+/*
+ *  parameters for sysproc.c
+ */
+#define AOUT_MAGIC	L_MAGIC
+
+/*
+ *  machine dependent definitions used by ../port/dat.h
+ */
+
+struct Lock
+{
+	ulong	key;			/* semaphore (non-zero = locked) */
+	ulong	sr;
+	ulong	pc;
+	Proc	*p;
+	ulong	pid;
+	ushort	isilock;
+};
+
+struct Label
+{
+	ulong	sp;
+	ulong	pc;
+};
+
+/*
+ * FPsave.fpstatus
+ */
+enum
+{
+	FPinit,
+	FPactive,
+	FPinactive,
+};
+
+struct	FPsave
+{
+	long	fpreg[2*32];
+	long	dummy;		/* lower bits of FPCR, useless */
+	long	fpstatus;
+};
+
+struct Conf
+{
+	ulong	nmach;		/* processors */
+	ulong	nproc;		/* processes */
+	ulong	npage0;		/* total physical pages of memory */
+	ulong	npage1;		/* total physical pages of memory */
+	ulong	npage;		/* total physical pages of memory */
+	ulong	base0;		/* base of bank 0 */
+	ulong	base1;		/* base of bank 1 */
+	ulong	upages;		/* user page pool */
+	ulong	nimage;		/* number of page cache image headers */
+	ulong	nswap;		/* number of swap pages */
+	int	nswppo;		/* max # of pageouts per segment pass */
+	ulong	copymode;	/* 0 is copy on write, 1 is copy on reference */
+	ulong	ptebase;
+	ulong	mbytes;
+	int	monitor;		/* has display? */
+	ulong	ialloc;		/* bytes available for interrupt time allocation */
+	ulong	pipeqsize;	/* size in bytes of pipe queues */
+};
+
+/*
+ *  mmu goo in the Proc structure
+ */
+struct PMMU
+{
+	Page	*mmutop;	/* 1st level table */
+	Page	*mmulvl2;	/* 2nd level table */
+	Page	*mmufree;	/* unused page table pages */
+	Page	*mmuused;	/* used page table pages, except for mmustk */
+};
+
+/*
+ *  things saved in the Proc structure during a notify
+ */
+struct Notsave
+{
+	ulong	UNUSED;
+};
+
+#include "../port/portdat.h"
+
+/*
+ *  machine dependent definitions not used by ../port/dat.h
+ */
+/*
+ * Fake kmap
+ */
+typedef	void		KMap;
+#define	VA(k)		((ulong)(k))
+#define	kmap(p)		(KMap*)((p)->pa|KZERO)
+#define	kunmap(k)
+
+/*
+ *	Process Control Block, used by PALcode
+ */
+struct PCB {
+	uvlong	ksp;
+	uvlong	usp;
+	uvlong	ptbr;
+	ulong	asn;
+	ulong	pcc;
+	uvlong	unique;
+	ulong	fen;
+	ulong	dummy;
+	uvlong	rsrv1;
+	uvlong	rsrv2;
+};
+
+struct Mach
+{
+	/* OFFSETS OF THE FOLLOWING KNOWN BY l.s */
+	int	machno;			/* physical id of processor */
+	ulong	splpc;			/* pc that called splhi() */
+	Proc	*proc;			/* current process on this processor */
+
+	/* ordering from here on irrelevant */
+	int	tlbfault;			/* only used by devproc; no access to tlb */
+	int	tlbpurge;			/* ... */
+	ulong	ticks;			/* of the clock since boot time */
+	Label	sched;			/* scheduler wakeup */
+	Lock	alarmlock;		/* access to alarm list */
+	void	*alarm;			/* alarms bound to this clock */
+	Page	*ufreeme;		/* address of upage of exited process */
+	int	speed;			/* cpu speed */
+	ulong	delayloop;		/* for the delay() routine */
+	int	nrdy;
+	ulong	fairness;		/* for runproc */
+
+	int	pfault;
+	int	cs;
+	int	syscall;
+	int	load;
+	int	intr;
+	int	nettime;
+	int	flushmmu;		/* make current proc flush it's mmu state */
+
+	PCB;
+
+	/* MUST BE LAST */
+	int	stack[1];
+};
+
+struct
+{
+	Lock;
+	short	machs;
+	short	exiting;
+	short	ispanic;
+}active;
+
+/*
+ *	Implementation-dependant functions (outside of Alpha architecture proper).
+ *	Called PCArch because that's what mkdevc calls it (for the PC).
+ */
+struct PCArch
+{
+	char*	id;
+	int	(*ident)(void);
+
+	void	(*coreinit)(void);		/* set up core logic, PCI mappings etc */
+	void	(*corehello)(void);		/* identify core logic to user */
+	void	(*coredetach)(void);		/* restore core logic before return to console */
+	void	*(*pcicfg)(int, int);		/* map and point to PCI cfg space */
+	void	*(*pcimem)(int, int);		/* map and point to PCI memory space */
+	void	(*intr)(Ureg*);
+	int	(*intrenable)(int, void (*)(Ureg*, void*), void*, int);
+
+	int		(*_inb)(int);
+	ushort	(*_ins)(int);
+	ulong	(*_inl)(int);
+	void		(*_outb)(int, int);
+	void		(*_outs)(int, ushort);
+	void		(*_outl)(int, ulong);
+	void		(*_insb)(int, void*, int);
+	void		(*_inss)(int, void*, int);
+	void		(*_insl)(int, void*, int);
+	void		(*_outsb)(int, void*, int);
+	void		(*_outss)(int, void*, int);
+	void		(*_outsl)(int, void*, int);
+};
+
+/*
+ *  a parsed plan9.ini line
+ */
+#define ISAOPTLEN	16
+#define NISAOPT		8
+
+struct ISAConf {
+	char	type[NAMELEN];
+	ulong	port;
+	ulong	irq;
+	ulong	dma;
+	ulong	mem;
+	ulong	size;
+	ulong	freq;
+
+	int	nopt;
+	char	opt[NISAOPT][ISAOPTLEN];
+};
+
+extern PCArch	*arch;
+
+#define	MACHP(n)	((Mach *)((int)&mach0+n*BY2PG))
+extern Mach		mach0;
+
+extern register Mach	*m;
+extern register Proc	*up;

@@ 0,0 1,436 @@
+#include "u.h"
+#include "../port/lib.h"
+#include "mem.h"
+#include "dat.h"
+#include "fns.h"
+#include "io.h"
+#include "ureg.h"
+#include "../port/error.h"
+#include "../port/netif.h"
+
+#include "etherif.h"
+
+static Ether *etherxx[MaxEther];
+
+Chan*
+etherattach(char* spec)
+{
+	ulong ctlrno;
+	char *p;
+	Chan *chan;
+
+	ctlrno = 0;
+	if(spec && *spec){
+		ctlrno = strtoul(spec, &p, 0);
+		if((ctlrno == 0 && p == spec) || *p || (ctlrno >= MaxEther))
+			error(Ebadarg);
+	}
+	if(etherxx[ctlrno] == 0)
+		error(Enodev);
+
+	chan = devattach('l', spec);
+	chan->dev = ctlrno;
+	if(etherxx[ctlrno]->attach)
+		etherxx[ctlrno]->attach(etherxx[ctlrno]);
+	return chan;
+}
+
+static int
+etherwalk(Chan* chan, char* name)
+{
+	return netifwalk(etherxx[chan->dev], chan, name);
+}
+
+static void
+etherstat(Chan* chan, char* dp)
+{
+	netifstat(etherxx[chan->dev], chan, dp);
+}
+
+static Chan*
+etheropen(Chan* chan, int omode)
+{
+	return netifopen(etherxx[chan->dev], chan, omode);
+}
+
+static void
+ethercreate(Chan*, char*, int, ulong)
+{
+}
+
+static void
+etherclose(Chan* chan)
+{
+	netifclose(etherxx[chan->dev], chan);
+}
+
+static long
+etherread(Chan* chan, void* buf, long n, vlong off)
+{
+	Ether *ether;
+	ulong offset = off;
+
+	ether = etherxx[chan->dev];
+	if((chan->qid.path & CHDIR) == 0 && ether->ifstat){
+		/*
+		 * With some controllers it is necessary to reach
+		 * into the chip to extract statistics.
+		 */
+		if(NETTYPE(chan->qid.path) == Nifstatqid)
+			return ether->ifstat(ether, buf, n, offset);
+		else if(NETTYPE(chan->qid.path) == Nstatqid)
+			ether->ifstat(ether, buf, 0, offset);
+	}
+
+	return netifread(ether, chan, buf, n, offset);
+}
+
+static Block*
+etherbread(Chan* chan, long n, ulong offset)
+{
+	return netifbread(etherxx[chan->dev], chan, n, offset);
+}
+
+static void
+etherremove(Chan*)
+{
+}
+
+static void
+etherwstat(Chan* chan, char* dp)
+{
+	netifwstat(etherxx[chan->dev], chan, dp);
+}
+
+static void
+etherrtrace(Netfile* f, Etherpkt* pkt, int len)
+{
+	int i, n;
+	Block *bp;
+
+	if(qwindow(f->in) <= 0)
+		return;
+	if(len > 64)
+		n = 64;
+	else
+		n = len;
+	bp = iallocb(n);
+	if(bp == 0)
+		return;
+	memmove(bp->wp, pkt->d, n);
+	i = TK2MS(MACHP(0)->ticks);
+	bp->wp[58] = len>>8;
+	bp->wp[59] = len;
+	bp->wp[60] = i>>24;
+	bp->wp[61] = i>>16;
+	bp->wp[62] = i>>8;
+	bp->wp[63] = i;
+	bp->wp += 64;
+	qpass(f->in, bp);
+}
+
+Block*
+etheriq(Ether* ether, Block* bp, int freebp)
+{
+	Etherpkt *pkt;
+	ushort type;
+	int len;
+	Netfile **ep, *f, **fp, *fx;
+	Block *xbp;
+
+	ether->inpackets++;
+
+	pkt = (Etherpkt*)bp->rp;
+	len = BLEN(bp);
+	type = (pkt->type[0]<<8)|pkt->type[1];
+	fx = 0;
+	ep = &ether->f[Ntypes];
+
+	/* check for valid multcast addresses */
+	if((pkt->d[0] & 1) && memcmp(pkt->d, ether->bcast, sizeof(pkt->d)) && ether->prom == 0){
+		if(!activemulti(ether, pkt->d, sizeof(pkt->d))){
+			if(freebp){
+				freeb(bp);
+				bp = 0;
+			}
+			return bp;
+		}
+	}
+
+	/*
+	 * Multiplex the packet to all the connections which want it.
+	 * If the packet is not to be used subsequently (freebp != 0),
+	 * attempt to simply pass it into one of the connections, thereby
+	 * saving a copy of the data (usual case hopefully).
+	 */
+	for(fp = ether->f; fp < ep; fp++){
+		if((f = *fp) && (f->type == type || f->type < 0)){
+			if(f->type > -2){
+				if(freebp && fx == 0)
+					fx = f;
+				else if(xbp = iallocb(len)){
+					memmove(xbp->wp, pkt, len);
+					xbp->wp += len;
+					qpass(f->in, xbp);
+				}
+				else
+					ether->soverflows++;
+			}
+			else
+				etherrtrace(f, pkt, len);
+		}
+	}
+
+	if(fx){
+		qpass(fx->in, bp);
+		return 0;
+	}
+	if(freebp){
+		freeb(bp);
+		return 0;
+	}
+
+	return bp;
+}
+
+static int
+etheroq(Ether* ether, Block* bp)
+{
+	int len, loopback, s;
+	Etherpkt *pkt;
+
+	ether->outpackets++;
+
+	/*
+	 * Check if the packet has to be placed back onto the input queue,
+	 * i.e. if it's a loopback or broadcast packet or the interface is
+	 * in promiscuous mode.
+	 * If it's a loopback packet indicate to etheriq that the data isn't
+	 * needed and return, etheriq will pass-on or free the block.
+	 */
+	pkt = (Etherpkt*)bp->rp;
+	len = BLEN(bp);
+	loopback = (memcmp(pkt->d, ether->ea, sizeof(pkt->d)) == 0);
+	if(loopback || memcmp(pkt->d, ether->bcast, sizeof(pkt->d)) == 0 || ether->prom){
+		s = splhi();
+		etheriq(ether, bp, loopback);
+		splx(s);
+	}
+
+	if(!loopback){
+		qbwrite(ether->oq, bp);
+		ether->transmit(ether);
+	}
+
+	return len;
+}
+
+static long
+etherwrite(Chan* chan, void* buf, long n, vlong)
+{
+	Ether *ether;
+	Block *bp;
+
+	ether = etherxx[chan->dev];
+	if(NETTYPE(chan->qid.path) != Ndataqid)
+		return netifwrite(ether, chan, buf, n);
+
+	if(n > ETHERMAXTU)
+		error(Etoobig);
+	if(n < ETHERMINTU)
+		error(Etoosmall);
+
+	bp = allocb(n);
+	if(waserror()){
+		freeb(bp);
+		nexterror();
+	}
+	memmove(bp->rp, buf, n);
+	memmove(bp->rp+Eaddrlen, ether->ea, Eaddrlen);
+	poperror();
+	bp->wp += n;
+
+	return etheroq(ether, bp);
+}
+
+static long
+etherbwrite(Chan* chan, Block* bp, ulong)
+{
+	Ether *ether;
+	long n;
+
+	n = BLEN(bp);
+	ether = etherxx[chan->dev];
+	if(NETTYPE(chan->qid.path) != Ndataqid){
+		n = netifwrite(ether, chan, bp->rp, n);
+		freeb(bp);
+		return n;
+	}
+
+	if(n > ETHERMAXTU){
+		freeb(bp);
+		error(Ebadarg);
+	}
+	if(n < ETHERMINTU){
+		freeb(bp);
+		error(Etoosmall);
+	}
+
+	return etheroq(ether, bp);
+}
+
+static struct {
+	char*	type;
+	int	(*reset)(Ether*);
+} cards[MaxEther+1];
+
+void
+addethercard(char* t, int (*r)(Ether*))
+{
+	static int ncard;
+
+	if(ncard == MaxEther)
+		panic("too many ether cards");
+	cards[ncard].type = t;
+	cards[ncard].reset = r;
+	ncard++;
+}
+
+int
+parseether(uchar *to, char *from)
+{
+	char nip[4];
+	char *p;
+	int i;
+
+	p = from;
+	for(i = 0; i < 6; i++){
+		if(*p == 0)
+			return -1;
+		nip[0] = *p++;
+		if(*p == 0)
+			return -1;
+		nip[1] = *p++;
+		nip[2] = 0;
+		to[i] = strtoul(nip, 0, 16);
+		if(*p == ':')
+			p++;
+	}
+	return 0;
+}
+
+static void
+etherreset(void)
+{
+	Ether *ether;
+	int i, n, ctlrno;
+	char name[NAMELEN], buf[128];
+
+	for(ether = 0, ctlrno = 0; ctlrno < MaxEther; ctlrno++){
+		if(ether == 0)
+			ether = malloc(sizeof(Ether));
+		memset(ether, 0, sizeof(Ether));
+		ether->ctlrno = ctlrno;
+		ether->tbdf = BUSUNKNOWN;
+		ether->mbps = 10;
+		if(isaconfig("ether", ctlrno, ether) == 0)
+			continue;
+		for(n = 0; cards[n].type; n++){
+			if(cistrcmp(cards[n].type, ether->type))
+				continue;
+			for(i = 0; i < ether->nopt; i++){
+				if(strncmp(ether->opt[i], "ea=", 3))
+					continue;
+				if(parseether(ether->ea, &ether->opt[i][3]) == -1)
+					memset(ether->ea, 0, Eaddrlen);
+			}	
+			if(cards[n].reset(ether))
+				break;
+
+			/*
+			 * IRQ2 doesn't really exist, it's used to gang the interrupt
+			 * controllers together. A device set to IRQ2 will appear on
+			 * the second interrupt controller as IRQ9.
+			 */
+			if(ether->irq == 2)
+				ether->irq = 9;
+			intrenable(VectorPCI+ether->irq, ether->interrupt, ether, ether->tbdf);
+
+			i = sprint(buf, "#l%d: %s: %dMbps port 0x%luX irq %d",
+				ctlrno, ether->type, ether->mbps, ether->port, ether->irq);
+			if(ether->mem)
+				i += sprint(buf+i, " addr 0x%luX", PADDR(ether->mem));
+			if(ether->size)
+				i += sprint(buf+i, " size 0x%luX", ether->size);
+			i += sprint(buf+i, ": %2.2uX%2.2uX%2.2uX%2.2uX%2.2uX%2.2uX",
+				ether->ea[0], ether->ea[1], ether->ea[2],
+				ether->ea[3], ether->ea[4], ether->ea[5]);
+			sprint(buf+i, "\n");
+			print(buf);
+
+			snprint(name, sizeof(name), "ether%d", ctlrno);
+			if(ether->mbps == 100){
+				netifinit(ether, name, Ntypes, 256*1024);
+				if(ether->oq == 0)
+					ether->oq = qopen(256*1024, 1, 0, 0);
+			}
+			else{
+				netifinit(ether, name, Ntypes, 65*1024);
+				if(ether->oq == 0)
+					ether->oq = qopen(65*1024, 1, 0, 0);
+			}
+			if(ether->oq == 0)
+				panic("etherreset %s", name);
+			ether->alen = Eaddrlen;
+			memmove(ether->addr, ether->ea, Eaddrlen);
+			memset(ether->bcast, 0xFF, Eaddrlen);
+
+			etherxx[ctlrno] = ether;
+			ether = 0;
+			break;
+		}
+	}
+	if(ether)
+		free(ether);
+}
+
+#define POLY 0xedb88320
+
+/* really slow 32 bit crc for ethers */
+ulong
+ethercrc(uchar *p, int len)
+{
+	int i, j;
+	ulong crc, b;
+
+	crc = 0xffffffff;
+	for(i = 0; i < len; i++){
+		b = *p++;
+		for(j = 0; j < 8; j++){
+			crc = (crc>>1) ^ (((crc^b) & 1) ? POLY : 0);
+			b >>= 1;
+		}
+	}
+	return crc;
+}
+
+Dev etherdevtab = {
+	'l',
+	"ether",
+
+	etherreset,
+	devinit,
+	etherattach,
+	devclone,
+	etherwalk,
+	etherstat,
+	etheropen,
+	ethercreate,
+	etherclose,
+	etherread,
+	etherbread,
+	etherwrite,
+	etherbwrite,
+	etherremove,
+	etherwstat,
+};

@@ 0,0 1,1057 @@
+#include	"u.h"
+#include	"../port/lib.h"
+#include	"mem.h"
+#include	"dat.h"
+#include	"fns.h"
+#include	"io.h"
+#include	"../port/error.h"
+
+#include	"floppy.h"
+
+/* Intel 82077A (8272A compatible) floppy controller */
+
+/* This module expects the following functions to be defined
+ * elsewhere: 
+ * 
+ * inb()
+ * outb()
+ * floppyexec()
+ * floppyeject() 
+ * floppysetup0()
+ * floppysetup1()
+ * dmainit()
+ * dmasetup()
+ * dmaend()
+ * 
+ * On DMA systems, floppyexec() should be an empty function; 
+ * on non-DMA systems, dmaend() should be an empty function; 
+ * dmasetup() may enforce maximum transfer sizes. 
+ */
+
+enum {
+	/* file types */
+	Qdir=		0, 
+	Qdata=		(1<<2),
+	Qctl=		(2<<2),
+	Qmask=		(3<<2),
+
+	DMAchan=	2,	/* floppy dma channel */
+};
+
+#define DPRINT if(floppydebug)print
+int floppydebug = 0;
+
+/*
+ *  types of drive (from PC equipment byte)
+ */
+enum
+{
+	Tnone=		0,
+	T360kb=		1,
+	T1200kb=	2,
+	T720kb=		3,
+	T1440kb=	4,
+};
+
+FType floppytype[] =
+{
+ { "3½HD",	T1440kb, 512, 18, 2, 1, 80, 0x1B, 0x54,	0, },
+ { "3½DD",	T1440kb, 512,  9, 2, 1, 80, 0x1B, 0x54, 2, },
+ { "3½DD",	T720kb,  512,  9, 2, 1, 80, 0x1B, 0x54, 2, },
+ { "5¼HD",	T1200kb, 512, 15, 2, 1, 80, 0x2A, 0x50, 0, },
+ { "5¼DD",	T1200kb, 512,  9, 2, 2, 40, 0x2A, 0x50, 1, },
+ { "ATT3B1",	T1200kb, 512,  8, 2, 2, 48, 0x2A, 0x50, 1, },
+ { "5¼DD",	T360kb,  512,  9, 2, 1, 40, 0x2A, 0x50, 2, },
+};
+
+/*
+ *  bytes per sector encoding for the controller.
+ *  - index for b2c is is (bytes per sector/128).
+ *  - index for c2b is code from b2c
+ */
+static int b2c[] =
+{
+[1]	0,
+[2]	1,
+[4]	2,
+[8]	3,
+};
+static int c2b[] =
+{
+	128,
+	256,
+	512,
+	1024,
+};
+
+FController	fl;
+
+#define MOTORBIT(i)	(1<<((i)+4))
+
+/*
+ *  predeclared
+ */
+static int	cmddone(void*);
+static void	floppyformat(FDrive*, char*);
+static void	floppykproc(void*);
+static void	floppypos(FDrive*,long);
+static int	floppyrecal(FDrive*);
+static int	floppyresult(void);
+static void	floppyrevive(void);
+static long	floppyseek(FDrive*, long);
+static int	floppysense(void);
+static void	floppywait(void);
+static long	floppyxfer(FDrive*, int, void*, long, long);
+
+Dirtab floppydir[]={
+	"fd0disk",		{Qdata + 0},	0,	0660,
+	"fd0ctl",		{Qctl + 0},	0,	0660,
+	"fd1disk",		{Qdata + 1},	0,	0660,
+	"fd1ctl",		{Qctl + 1},	0,	0660,
+	"fd2disk",		{Qdata + 2},	0,	0660,
+	"fd2ctl",		{Qctl + 2},	0,	0660,
+	"fd3disk",		{Qdata + 3},	0,	0660,
+	"fd3ctl",		{Qctl + 3},	0,	0660,
+};
+#define NFDIR	2	/* directory entries/drive */
+
+static void
+fldump(void)
+{
+mb();
+	DPRINT("sra %ux srb %ux dor %ux msr %ux dir %ux\n", inb(Psra), inb(Psrb),
+		inb(Pdor), inb(Pmsr), inb(Pdir));
+mb();
+}
+
+/*
+ *  set floppy drive to its default type
+ */
+static void
+floppysetdef(FDrive *dp)
+{
+	FType *t;
+
+	for(t = floppytype; t < &floppytype[nelem(floppytype)]; t++)
+		if(dp->dt == t->dt){
+			dp->t = t;
+			floppydir[NFDIR*dp->dev].length = dp->t->cap;
+			break;
+		}
+}
+
+static void
+floppyreset(void)
+{
+	FDrive *dp;
+	FType *t;
+	ulong maxtsize;
+
+	dmainit(DMAchan);
+	
+	floppysetup0(&fl);
+
+	/*
+	 *  init dependent parameters
+	 */
+	maxtsize = 0;
+	for(t = floppytype; t < &floppytype[nelem(floppytype)]; t++){
+		t->cap = t->bytes * t->heads * t->sectors * t->tracks;
+		t->bcode = b2c[t->bytes/128];
+		t->tsize = t->bytes * t->sectors;
+		if(maxtsize < t->tsize)
+			maxtsize = t->tsize;
+	}
+
+	/*
+	 *  allocate the drive storage
+	 */
+	fl.d = xalloc(fl.ndrive*sizeof(FDrive));
+	fl.selected = fl.d;
+
+	/*
+	 *  stop the motors
+	 */
+	fl.motor = 0;
+	delay(10);
+mb();
+	outb(Pdor, fl.motor | Fintena | Fena);
+mb();
+	delay(10);
+
+	/*
+	 *  init drives
+	 */
+	for(dp = fl.d; dp < &fl.d[fl.ndrive]; dp++){
+		dp->dev = dp - fl.d;
+		dp->dt = T1440kb;
+		floppysetdef(dp);
+		dp->cyl = -1;			/* because we don't know */
+		dp->cache = (uchar*)xspanalloc(maxtsize, BY2PG, 64*1024);
+		dp->ccyl = -1;
+		dp->vers = 0;
+	}
+
+	/*
+	 *  first operation will recalibrate
+	 */
+	fl.confused = 1;
+
+	floppysetup1(&fl);
+}
+
+static Chan*
+floppyattach(char *spec)
+{
+	static int kstarted;
+
+	if(kstarted == 0){
+		/*
+		 *  watchdog to turn off the motors
+		 */
+		kstarted = 1;
+		kproc("floppy", floppykproc, 0);
+	}
+	return devattach('f', spec);
+}
+
+static int
+floppywalk(Chan *c, char *name)
+{
+	return devwalk(c, name, floppydir, fl.ndrive*NFDIR, devgen);
+}
+
+static void
+floppystat(Chan *c, char *dp)
+{
+	devstat(c, dp, floppydir, fl.ndrive*NFDIR, devgen);
+}
+
+static Chan*
+floppyopen(Chan *c, int omode)
+{
+	return devopen(c, omode, floppydir, fl.ndrive*NFDIR, devgen);
+}
+
+static void
+floppyclose(Chan *)
+{
+}
+
+static void
+islegal(ulong offset, long n, FDrive *dp)
+{
+	if(offset % dp->t->bytes)
+		error(Ebadarg);
+	if(n % dp->t->bytes)
+		error(Ebadarg);
+}
+
+/*
+ *  check if the floppy has been replaced under foot.  cause
+ *  an error if it has.
+ *
+ *  a seek and a read clears the condition.  this was determined
+ *  experimentally, there has to be a better way.
+ *
+ *  if the read fails, cycle through the possible floppy
+ *  density till one works or we've cycled through all
+ *  possibilities for this drive.
+ */
+static void
+changed(Chan *c, FDrive *dp)
+{
+	ulong old;
+	FType *start;
+
+	/*
+	 *  if floppy has changed or first time through
+	 */
+mb();
+	if((inb(Pdir)&Fchange) || dp->vers == 0){
+mb();
+		DPRINT("changed\n");
+		fldump();
+		dp->vers++;
+		floppysetdef(dp);
+		start = dp->t;
+		dp->confused = 1;	/* make floppyon recal */
+DPRINT("b4 floppyon:\n");
+fldump();
+		floppyon(dp);
+DPRINT("after floppyon:\n");
+fldump();
+		floppyseek(dp, dp->t->heads*dp->t->tsize);
+DPRINT("after floppyseek:\n");
+fldump();
+		while(waserror()){
+			while(++dp->t){
+				if(dp->t == &floppytype[nelem(floppytype)])
+					dp->t = floppytype;
+				if(dp->dt == dp->t->dt)
+					break;
+			}
+			floppydir[NFDIR*dp->dev].length = dp->t->cap;
+			floppyon(dp);
+			DPRINT("changed: trying %s\n", dp->t->name);
+			fldump();
+			if(dp->t == start)
+				nexterror();
+		}
+		floppyxfer(dp, Fread, dp->cache, 0, dp->t->tsize);
+		poperror();
+	}
+
+	old = c->qid.vers;
+	c->qid.vers = dp->vers;
+	if(old && old != dp->vers)
+		error(Eio);
+}
+
+static int
+readtrack(FDrive *dp, int cyl, int head)
+{
+	int i, nn, sofar;
+	ulong pos;
+
+	nn = dp->t->tsize;
+	if(dp->ccyl==cyl && dp->chead==head)
+		return nn;
+	pos = (cyl*dp->t->heads+head) * nn;
+	for(sofar = 0; sofar < nn; sofar += i){
+		dp->ccyl = -1;
+		i = floppyxfer(dp, Fread, dp->cache + sofar, pos + sofar, nn - sofar);
+		if(i <= 0)
+			return -1;
+	}
+	dp->ccyl = cyl;
+	dp->chead = head;
+	return nn;
+}
+
+static long
+floppyread(Chan *c, void *a, long n, vlong off)
+{
+	FDrive *dp;
+	long rv;
+	int sec, head, cyl;
+	long len;
+	uchar *aa;
+	ulong offset = off;
+
+	if(c->qid.path == CHDIR)
+		return devdirread(c, a, n, floppydir, fl.ndrive*NFDIR, devgen);
+
+	rv = 0;
+	dp = &fl.d[c->qid.path & ~Qmask];
+	switch ((int)(c->qid.path & Qmask)) {
+	case Qdata:
+		islegal(offset, n, dp);
+		aa = a;
+
+		qlock(&fl);
+		if(waserror()){
+			qunlock(&fl);
+			nexterror();
+		}
+		floppyon(dp);
+		changed(c, dp);
+		for(rv = 0; rv < n; rv += len){
+			/*
+			 *  all xfers come out of the track cache
+			 */
+			dp->len = n - rv;
+			floppypos(dp, offset+rv);
+			cyl = dp->tcyl;
+			head = dp->thead;
+			len = dp->len;
+			sec = dp->tsec;
+			if(readtrack(dp, cyl, head) < 0)
+				break;
+			memmove(aa+rv, dp->cache + (sec-1)*dp->t->bytes, len);
+		}
+		qunlock(&fl);
+		poperror();
+
+		break;
+	case Qctl:
+		return readstr(offset, a, n, dp->t->name);
+	default:
+		panic("floppyread: bad qid");
+	}
+
+	return rv;
+}
+
+#define SNCMP(a, b) strncmp(a, b, sizeof(b)-1)
+static long
+floppywrite(Chan *c, void *a, long n, vlong off)
+{
+	FDrive *dp;
+	long rv, i;
+	char *aa = a;
+	char ctlmsg[64];
+	ulong offset = off;
+
+	rv = 0;
+	dp = &fl.d[c->qid.path & ~Qmask];
+	switch ((int)(c->qid.path & Qmask)) {
+	case Qdata:
+		islegal(offset, n, dp);
+		qlock(&fl);
+		if(waserror()){
+			qunlock(&fl);
+			nexterror();
+		}
+		floppyon(dp);
+		changed(c, dp);
+		for(rv = 0; rv < n; rv += i){
+			floppypos(dp, offset+rv);
+			if(dp->tcyl == dp->ccyl)
+				dp->ccyl = -1;
+			i = floppyxfer(dp, Fwrite, aa+rv, offset+rv, n-rv);
+			if(i < 0)
+				break;
+			if(i == 0)
+				error(Eio);
+		}
+		qunlock(&fl);
+		poperror();
+		break;
+	case Qctl:
+		rv = n;
+		qlock(&fl);
+		if(waserror()){
+			qunlock(&fl);
+			nexterror();
+		}
+		if(n >= sizeof(ctlmsg))
+			n = sizeof(ctlmsg) - 1;
+		memmove(ctlmsg, aa, n);
+		ctlmsg[n] = 0;
+		if(SNCMP(ctlmsg, "eject") == 0){
+			floppyeject(dp);
+		} else if(SNCMP(ctlmsg, "reset") == 0){
+			fl.confused = 1;
+			floppyon(dp);
+		} else if(SNCMP(ctlmsg, "format") == 0){
+			floppyformat(dp, ctlmsg);
+		} else if(SNCMP(ctlmsg, "debug") == 0){
+			floppydebug = 1;
+		} else
+			error(Ebadctl);
+		poperror();
+		qunlock(&fl);
+		break;
+	default:
+		panic("floppywrite: bad qid");
+	}
+
+	return rv;
+}
+
+static void
+floppykproc(void *)
+{
+	FDrive *dp;
+
+	while(waserror())
+		;
+	for(;;){
+		for(dp = fl.d; dp < &fl.d[fl.ndrive]; dp++){
+			if((fl.motor&MOTORBIT(dp->dev))
+			&& TK2SEC(m->ticks - dp->lasttouched) > 5
+			&& canqlock(&fl)){
+				if(TK2SEC(m->ticks - dp->lasttouched) > 5)
+					floppyoff(dp);
+				qunlock(&fl);
+			}
+		}
+		tsleep(&fl.kr, return0, 0, 1000);
+	}
+}
+
+/*
+ *  start a floppy drive's motor.
+ */
+static void
+floppyon(FDrive *dp)
+{
+	int alreadyon;
+	int tries;
+
+	if(fl.confused)
+		floppyrevive();
+
+	/* start motor and select drive */
+	alreadyon = fl.motor & MOTORBIT(dp->dev);
+	fl.motor |= MOTORBIT(dp->dev);
+mb();
+	outb(Pdor, fl.motor | Fintena | Fena | dp->dev);
+mb();
+	if(!alreadyon){
+		/* wait for drive to spin up */
+		tsleep(&dp->r, return0, 0, 750);
+
+		/* clear any pending interrupts */
+		floppysense();
+	}
+
+	/* set transfer rate */
+	if(fl.rate != dp->t->rate){
+		fl.rate = dp->t->rate;
+mb();
+		outb(Pdsr, fl.rate);
+mb();
+	}
+
+	/* get drive to a known cylinder */
+	if(dp->confused)
+		for(tries = 0; tries < 4; tries++)
+			if(floppyrecal(dp) >= 0)
+				break;
+	dp->lasttouched = m->ticks;
+	fl.selected = dp;
+}
+
+/*
+ *  stop the floppy if it hasn't been used in 5 seconds
+ */
+static void
+floppyoff(FDrive *dp)
+{
+	fl.motor &= ~MOTORBIT(dp->dev);
+mb();
+	outb(Pdor, fl.motor | Fintena | Fena | dp->dev);
+mb();
+}
+
+/*
+ *  send a command to the floppy
+ */
+static int
+floppycmd(void)
+{
+	int i;
+	int tries;
+
+	fl.nstat = 0;
+	for(i = 0; i < fl.ncmd; i++){
+		for(tries = 0; ; tries++){
+mb();
+			if((inb(Pmsr)&(Ffrom|Fready)) == Fready)
+				break;
+mb();
+			if(tries > 1000){
+				DPRINT("cmd %ux can't be sent (%d)\n", fl.cmd[0], i);
+				fldump();
+
+				/* empty fifo, might have been a bad command */
+				floppyresult();
+				return -1;
+			}
+			microdelay(8);	/* for machine independence */
+		}
+mb();
+		outb(Pfdata, fl.cmd[i]);
+mb();
+	}
+	return 0;
+}
+
+/*
+ *  get a command result from the floppy
+ *
+ *  when the controller goes ready waiting for a command
+ *  (instead of sending results), we're done
+ * 
+ */
+static int
+floppyresult(void)
+{
+	int i, s;
+	int tries;
+
+	/* get the result of the operation */
+	for(i = 0; i < sizeof(fl.stat); i++){
+		/* wait for status byte */
+		for(tries = 0; ; tries++){
+mb();
+			s = inb(Pmsr)&(Ffrom|Fready);
+mb();
+			if(s == Fready){
+				fl.nstat = i;
+				return fl.nstat;
+			}
+			if(s == (Ffrom|Fready))
+				break;
+			if(tries > 1000){
+				DPRINT("floppyresult: %d stats\n", i);
+				fldump();
+				fl.confused = 1;
+				return -1;
+			}
+			microdelay(8);	/* for machine independence */
+		}
+mb();
+		fl.stat[i] = inb(Pfdata);
+mb();
+// print("stat[%d]: %.2ux\n", i, fl.stat[i]);
+	}
+	fl.nstat = sizeof(fl.stat);
+	return fl.nstat;
+}
+
+/*
+ *  calculate physical address of a logical byte offset into the disk
+ *
+ *  truncate dp->length if it crosses a track boundary
+ */
+static void
+floppypos(FDrive *dp, long off)
+{
+	int lsec;
+	int ltrack;
+	int end;
+
+	lsec = off/dp->t->bytes;
+	ltrack = lsec/dp->t->sectors;
+	dp->tcyl = ltrack/dp->t->heads;
+	dp->tsec = (lsec % dp->t->sectors) + 1;
+	dp->thead = (lsec/dp->t->sectors) % dp->t->heads;
+
+	/*
+	 *  can't read across track boundaries.
+	 *  if so, decrement the bytes to be read.
+	 */
+	end = (ltrack+1)*dp->t->sectors*dp->t->bytes;
+	if(off+dp->len > end)
+		dp->len = end - off;
+}
+
+/*
+ *  get the interrupt cause from the floppy.
+ */
+static int
+floppysense(void)
+{
+	fl.ncmd = 0;
+	fl.cmd[fl.ncmd++] = Fsense;
+	if(floppycmd() < 0)
+		return -1;
+	if(floppyresult() < 2){
+		DPRINT("can't read sense response\n");
+		fldump();
+		fl.confused = 1;
+		return -1;
+	}
+	return 0;
+}
+
+static int
+cmddone(void *)
+{
+	return fl.ncmd == 0;
+}
+
+/*
+ *  Wait for a floppy interrupt.  If none occurs in 5 seconds, we
+ *  may have missed one.  This only happens on some portables which
+ *  do power management behind our backs.  Call the interrupt
+ *  routine to try to clear any conditions.
+ */
+static void
+floppywait(void)
+{
+	tsleep(&fl.r, cmddone, 0, 5000);
+	if(!cmddone(0)){
+		floppyintr(0);
+		fl.confused = 1;
+	}
+}
+
+/*
+ *  we've lost the floppy position, go to cylinder 0.
+ */
+static int
+floppyrecal(FDrive *dp)
+{
+	dp->ccyl = -1;
+	dp->cyl = -1;
+
+	fl.ncmd = 0;
+	fl.cmd[fl.ncmd++] = Frecal;
+	fl.cmd[fl.ncmd++] = dp->dev;
+	if(floppycmd() < 0)
+		return -1;
+	floppywait();
+	if(fl.nstat < 2){
+mb();
+		DPRINT("recalibrate: confused %ux\n", inb(Pmsr));
+mb();
+		fl.confused = 1;
+		return -1;
+	}
+	if((fl.stat[0] & (Codemask|Seekend)) != Seekend){
+		DPRINT("recalibrate: failed\n");
+		dp->confused = 1;
+		return -1;
+	}
+	dp->cyl = fl.stat[1];
+	if(dp->cyl != 0){
+		DPRINT("recalibrate: wrong cylinder %d\n", dp->cyl);
+		dp->cyl = -1;
+		dp->confused = 1;
+		return -1;
+	}
+
+	dp->confused = 0;
+	return 0;
+}
+
+/*
+ *  if the controller or a specific drive is in a confused state,
+ *  reset it and get back to a kown state
+ */
+static void
+floppyrevive(void)
+{
+	FDrive *dp;
+
+	/*
+	 *  reset the controller if it's confused
+	 */
+	if(fl.confused){
+		DPRINT("floppyrevive in\n");
+		fldump();
+
+		/* reset controller and turn all motors off */
+		splhi();
+		fl.ncmd = 1;
+		fl.cmd[0] = 0;
+mb();
+		outb(Pdor, 0);
+mb();
+		delay(10);
+mb();
+		outb(Pdor, Fintena|Fena);
+mb();
+		delay(10);
+		spllo();
+		fl.motor = 0;
+		fl.confused = 0;
+		floppywait();
+
+		/* mark all drives in an unknown state */
+		for(dp = fl.d; dp < &fl.d[fl.ndrive]; dp++)
+			dp->confused = 1;
+
+		/* set rate to a known value */
+mb();
+		outb(Pdsr, 0);
+mb();
+		fl.rate = 0;
+
+		DPRINT("floppyrevive out\n");
+		fldump();
+	}
+}
+
+/*
+ *  seek to the target cylinder
+ *
+ *	interrupt, no results
+ */
+static long
+floppyseek(FDrive *dp, long off)
+{
+	floppypos(dp, off);
+	if(dp->cyl == dp->tcyl)
+		return dp->tcyl;
+	dp->cyl = -1;
+
+	fl.ncmd = 0;
+	fl.cmd[fl.ncmd++] = Fseek;
+	fl.cmd[fl.ncmd++] = (dp->thead<<2) | dp->dev;
+	fl.cmd[fl.ncmd++] = dp->tcyl * dp->t->steps;
+	if(floppycmd() < 0)
+		return -1;
+	floppywait();
+	if(fl.nstat < 2){
+		DPRINT("seek: confused\n");
+		fl.confused = 1;
+		return -1;
+	}
+	if((fl.stat[0] & (Codemask|Seekend)) != Seekend){
+		DPRINT("seek: failed\n");
+		dp->confused = 1;
+		return -1;
+	}
+
+	dp->cyl = dp->tcyl;
+	return dp->tcyl;
+}
+
+/*
+ *  read or write to floppy.  try up to three times.
+ */
+static long
+floppyxfer(FDrive *dp, int cmd, void *a, long off, long n)
+{
+	long offset;
+	int tries;
+
+	if(off >= dp->t->cap)
+		return 0;
+	if(off + n > dp->t->cap)
+		n = dp->t->cap - off;
+
+	/* retry on error (until it gets ridiculous) */
+	tries = 0;
+	while(waserror()){
+		if(tries++ > 20)
+			nexterror();
+		DPRINT("floppyxfer: retrying\n");
+		/*floppyon(dp);*/
+	}
+
+	dp->len = n;
+	if(floppyseek(dp, off) < 0){
+		DPRINT("xfer: seek failed\n");
+		dp->confused = 1;
+		error(Eio);
+	}
+
+	/*
+	 *  set up the dma (dp->len may be trimmed)
+	 */
+	if(waserror()){
+		dmaend(DMAchan);
+		nexterror();
+	}
+	dp->len = dmasetup(DMAchan, a, dp->len, cmd==Fread);
+	if(dp->len < 0)
+		error(Eio);
+
+	/*
+	 *  start operation
+	 */
+	fl.ncmd = 0;
+	fl.cmd[fl.ncmd++] = cmd | (dp->t->heads > 1 ? Fmulti : 0);
+	fl.cmd[fl.ncmd++] = (dp->thead<<2) | dp->dev;
+	fl.cmd[fl.ncmd++] = dp->tcyl;
+	fl.cmd[fl.ncmd++] = dp->thead;
+	fl.cmd[fl.ncmd++] = dp->tsec;
+	fl.cmd[fl.ncmd++] = dp->t->bcode;
+	fl.cmd[fl.ncmd++] = dp->t->sectors;
+	fl.cmd[fl.ncmd++] = dp->t->gpl;
+	fl.cmd[fl.ncmd++] = 0xFF;
+	if(floppycmd() < 0)
+		error(Eio);
+
+	/* Poll ready bits and transfer data */
+	floppyexec((char*)a, dp->len, cmd==Fread);
+
+	/*
+	 *  give bus to DMA, floppyintr() will read result
+	 */
+	floppywait();
+	dmaend(DMAchan);
+	poperror();
+
+	/*
+	 *  check for errors
+	 */
+	if(fl.nstat < 7){
+		DPRINT("xfer: confused\n");
+		fl.confused = 1;
+		error(Eio);
+	}
+	if((fl.stat[0] & Codemask)!=0 || fl.stat[1] || fl.stat[2]){
+		DPRINT("xfer: failed %ux %ux %ux\n", fl.stat[0],
+			fl.stat[1], fl.stat[2]);
+		DPRINT("offset %lud len %ld\n", off, dp->len);
+		if((fl.stat[0]&Codemask)==Cmdexec && fl.stat[1]==Overrun){
+			DPRINT("DMA overrun: retry\n");
+		} else
+			dp->confused = 1;
+		error(Eio);
+	}
+
+	/*
+	 *  check for correct cylinder
+	 */
+	offset = fl.stat[3] * dp->t->heads + fl.stat[4];
+	offset = offset*dp->t->sectors + fl.stat[5] - 1;
+	offset = offset * c2b[fl.stat[6]];
+	if(offset != off+dp->len){
+		DPRINT("xfer: ends on wrong cyl\n");
+		dp->confused = 1;
+		error(Eio);
+	}
+	poperror();
+
+	dp->lasttouched = m->ticks;
+	return dp->len;
+}
+
+/*
+ *  format a track
+ */
+static void
+floppyformat(FDrive *dp, char *params)
+{
+ 	int cyl, h, sec;
+	ulong track;
+	uchar *buf, *bp;
+	FType *t;
+	char *f[3];
+
+	/*
+	 *  set the type
+	 */
+	if(parsefields(params, f, 3, " ") > 1){
+		for(t = floppytype; t < &floppytype[nelem(floppytype)]; t++){
+			if(strcmp(f[1], t->name)==0 && t->dt==dp->dt){
+				dp->t = t;
+				floppydir[NFDIR*dp->dev].length = dp->t->cap;
+				break;
+			}
+		}
+		if(t >= &floppytype[nelem(floppytype)])
+			error(Ebadarg);
+	} else {
+		floppysetdef(dp);
+		t = dp->t;
+	}
+
+	/*
+	 *  buffer for per track info
+	 */
+	buf = smalloc(t->sectors*4);
+	if(waserror()){
+		free(buf);
+		nexterror();
+	}
+
+	/* force a recalibrate to cylinder 0 */
+	dp->confused = 1;
+	if(!waserror()){
+		floppyon(dp);
+		poperror();
+	}
+
+	/*
+	 *  format a track at time
+	 */
+	for(track = 0; track < t->tracks*t->heads; track++){
+		cyl = track/t->heads;
+		h = track % t->heads;
+
+		/*
+		 *  seek to track, ignore errors
+		 */
+		floppyseek(dp, track*t->tsize);
+		dp->cyl = cyl;
+		dp->confused = 0;
+
+		/*
+		 *  set up the dma (dp->len may be trimmed)
+		 */
+		bp = buf;
+		for(sec = 1; sec <= t->sectors; sec++){
+			*bp++ = cyl;
+			*bp++ = h;
+			*bp++ = sec;
+			*bp++ = t->bcode;
+		}
+		if(waserror()){
+			dmaend(DMAchan);
+			nexterror();
+		}
+		if(dmasetup(DMAchan, buf, bp-buf, 0) < 0)
+			error(Eio);
+
+		/*
+		 *  start operation
+		 */
+		fl.ncmd = 0;
+		fl.cmd[fl.ncmd++] = Fformat;
+		fl.cmd[fl.ncmd++] = (h<<2) | dp->dev;
+		fl.cmd[fl.ncmd++] = t->bcode;
+		fl.cmd[fl.ncmd++] = t->sectors;
+		fl.cmd[fl.ncmd++] = t->fgpl;
+		fl.cmd[fl.ncmd++] = 0x5a;
+		if(floppycmd() < 0)
+			error(Eio);
+
+		/* Poll ready bits and transfer data */
+		floppyexec((char *)buf, bp-buf, 0);
+
+		/*
+		 *  give bus to DMA, floppyintr() will read result
+		 */
+		floppywait();
+		dmaend(DMAchan);
+		poperror();
+
+		/*
+		 *  check for errors
+		 */
+		if(fl.nstat < 7){
+			DPRINT("format: confused\n");
+			fl.confused = 1;
+			error(Eio);
+		}
+		if((fl.stat[0]&Codemask)!=0 || fl.stat[1]|| fl.stat[2]){
+			DPRINT("format: failed %ux %ux %ux\n",
+				fl.stat[0], fl.stat[1], fl.stat[2]);
+			dp->confused = 1;
+			error(Eio);
+		}
+	}
+	free(buf);
+	dp->confused = 1;
+	poperror();
+}
+
+static void
+floppyintr(Ureg *)
+{
+	switch(fl.cmd[0]&~Fmulti){
+	case Fread:
+	case Fwrite:
+	case Fformat:
+	case Fdumpreg: 
+		floppyresult();
+		break;
+	case Fseek:
+	case Frecal:
+	default:
+		floppysense();	/* to clear interrupt */
+		break;
+	}
+	fl.ncmd = 0;
+	wakeup(&fl.r);
+}
+
+Dev floppydevtab = {
+	'f',
+	"floppy",
+
+	floppyreset,
+	devinit,
+	floppyattach,
+	devclone,
+	floppywalk,
+	floppystat,
+	floppyopen,
+	devcreate,
+	floppyclose,
+	floppyread,
+	devbread,
+	floppywrite,
+	devbwrite,
+	devremove,
+	devwstat,
+};

@@ 0,0 1,331 @@
+/*
+ */
+#include "u.h"
+#include "../port/lib.h"
+#include "mem.h"
+#include "dat.h"
+#include "fns.h"
+#include "io.h"
+#include "../port/error.h"
+
+#define	Image	IMAGE
+#include <draw.h>
+#include <memdraw.h>
+#include <cursor.h>
+#include "screen.h"
+
+enum {
+	Qdir,
+	Qvgaiob,
+	Qvgaiow,
+	Qvgaiol,
+	Qvgactl,
+};
+
+static Dirtab vgadir[] = {
+	"vgaiob",	{ Qvgaiob, 0 },		0,	0660,
+	"vgaiow",	{ Qvgaiow, 0 },		0,	0660,
+	"vgaiol",	{ Qvgaiol, 0 },		0,	0660,
+	"vgactl",	{ Qvgactl, 0 },		0,	0660,
+};
+
+static void
+vgareset(void)
+{
+	conf.monitor = 1;
+}
+
+static Chan*
+vgaattach(char* spec)
+{
+	if(*spec && strcmp(spec, "0"))
+		error(Eio);
+	return devattach('v', spec);
+}
+
+int
+vgawalk(Chan* c, char* name)
+{
+	return devwalk(c, name, vgadir, nelem(vgadir), devgen);
+}
+
+static void
+vgastat(Chan* c, char* dp)
+{
+	devstat(c, dp, vgadir, nelem(vgadir), devgen);
+}
+
+static Chan*
+vgaopen(Chan* c, int omode)
+{
+	return devopen(c, omode, vgadir, nelem(vgadir), devgen);
+}
+
+static void
+vgaclose(Chan*)
+{
+}
+
+static long
+vgaread(Chan* c, void* a, long n, vlong off)
+{
+	int len, port;
+	char *p, *s;
+	ushort *sp;
+	ulong *lp;
+	VGAscr *scr;
+	ulong offset = off;
+
+	switch(c->qid.path & ~CHDIR){
+
+	case Qdir:
+		return devdirread(c, a, n, vgadir, nelem(vgadir), devgen);
+
+	case Qvgactl:
+		scr = &vgascreen[0];
+
+		p = malloc(READSTR);
+		if(waserror()){
+			free(p);
+			nexterror();
+		}
+		if(scr->dev)
+			s = scr->dev->name;
+		else
+			s = "cga";
+		len = snprint(p, READSTR, "type: %s\n", s);
+		if(scr->gscreen)
+			len += snprint(p+len, READSTR-len, "size: %dx%dx%d\n",
+				scr->gscreen->r.max.x, scr->gscreen->r.max.y,
+				1<<scr->gscreen->ldepth);
+		if(scr->cur)
+			s = scr->cur->name;
+		else
+			s = "off";
+		len += snprint(p+len, READSTR-len, "hwgc: %s\n", s);
+		snprint(p+len, READSTR-len, "addr: 0x%lux\n", scr->aperture);
+
+		n = readstr(offset, a, n, p);
+		poperror();
+		free(p);
+
+		return n;
+
+	case Qvgaiob:
+		port = offset;
+		for(p = a; port < offset+n; port++)
+			*p++ = inb(port);
+		return n;
+
+	case Qvgaiow:
+		if((n & 0x01) || (offset & 0x01))
+			error(Ebadarg);
+		n /= 2;
+		sp = a;
+		for(port = offset; port < offset+n; port += 2)
+			*sp++ = ins(port);
+		return n*2;
+
+	case Qvgaiol:
+		if((n & 0x03) || (offset & 0x03))
+			error(Ebadarg);
+		n /= 4;
+		lp = a;
+		for(port = offset; port < offset+n; port += 4)
+			*lp++ = inl(port);
+		return n*4;
+
+	default:
+		error(Egreg);
+		break;
+	}
+
+	return 0;
+}
+
+static void
+vgactl(char* a)
+{
+	int align, i, n, size, x, y, z;
+	char *field[4], *p;
+	VGAscr *scr;
+	extern VGAdev *vgadev[];
+	extern VGAcur *vgacur[];
+
+	n = parsefields(a, field, 4, " ");
+	if(n < 2)
+		error(Ebadarg);
+
+	scr = &vgascreen[0];
+	if(strcmp(field[0], "hwgc") == 0){
+		if(n < 2)
+			error(Ebadarg);
+		if(strcmp(field[1], "off") == 0){
+			lock(&cursor);
+			if(scr->cur){
+				if(scr->cur->disable)
+					scr->cur->disable(scr);
+				scr->cur = nil;
+			}
+			unlock(&cursor);
+			return;
+		}
+
+		for(i = 0; vgacur[i]; i++){
+			if(strcmp(field[1], vgacur[i]->name))
+				continue;
+			lock(&cursor);
+			if(scr->cur && scr->cur->disable)
+				scr->cur->disable(scr);
+			scr->cur = vgacur[i];
+			if(scr->cur->enable)
+				scr->cur->enable(scr);
+			unlock(&cursor);
+			return;
+		}
+	}
+	else if(strcmp(field[0], "type") == 0){
+		if(n < 2)
+			error(Ebadarg);
+
+		for(i = 0; vgadev[i]; i++){
+			if(strcmp(field[1], vgadev[i]->name))
+				continue;
+			if(scr->dev && scr->dev->disable)
+				scr->dev->disable(scr);
+			scr->dev = vgadev[i];
+			if(scr->dev->enable)
+				scr->dev->enable(scr);
+			return;
+		}
+	}
+	else if(strcmp(field[0], "size") == 0){
+		if(n < 2)
+			error(Ebadarg);
+		x = strtoul(field[1], &p, 0);
+		if(x == 0 || x > 2048)
+			error(Ebadarg);
+		if(*p)
+			p++;
+
+		y = strtoul(p, &p, 0);
+		if(y == 0 || y > 2048)
+			error(Ebadarg);
+		if(*p)
+			p++;
+
+		switch(strtoul(p, &p, 0)){
+		case 8:
+			z = 3;
+			break;
+
+		default:
+			z = 0;
+			error(Ebadarg);
+		}
+
+		cursoroff(1);
+		if(screensize(x, y, z))
+			error(Egreg);
+		vgascreenwin(scr);
+		cursoron(1);
+		return;
+	}
+	else if(strcmp(field[0], "linear") == 0){
+		if(n < 2)
+			error(Ebadarg);
+
+		size = strtoul(field[1], 0, 0);
+		if(n < 3)
+			align = 0;
+		else
+			align = strtoul(field[2], 0, 0);
+		if(screenaperture(size, align))
+			error("not enough free address space");
+		return;
+	}
+
+	error(Ebadarg);
+}
+
+static long
+vgawrite(Chan* c, void* a, long n, vlong off)
+{
+	int port;
+	char *p;
+	ushort *sp;
+	ulong *lp;
+	ulong offset = off;
+
+	switch(c->qid.path & ~CHDIR){
+
+	case Qdir:
+		error(Eperm);
+
+	case Qvgactl:
+		if(offset || n >= READSTR)
+			error(Ebadarg);
+		p = malloc(READSTR);
+		if(waserror()){
+			free(p);
+			nexterror();
+		}
+		memmove(p, a, n);
+		p[n] = 0;
+		vgactl(p);
+		poperror();
+		free(p);
+		return n;
+
+	case Qvgaiob:
+		p = a;
+		for(port = offset; port < offset+n; port++)
+			outb(port, *p++);
+		return n;
+
+	case Qvgaiow:
+		if((n & 01) || (offset & 01))
+			error(Ebadarg);
+		n /= 2;
+		sp = a;
+		for(port = offset; port < offset+n; port += 2)
+			outs(port, *sp++);
+		return n*2;
+
+	case Qvgaiol:
+		if((n & 0x03) || (offset & 0x03))
+			error(Ebadarg);
+		n /= 4;
+		lp = a;
+		for(port = offset; port < offset+n; port += 4)
+			outl(port, *lp++);
+		return n*4;
+
+	default:
+		error(Egreg);
+		break;
+	}
+
+	return 0;
+}
+
+Dev vgadevtab = {
+	'v',
+	"vga",
+
+	vgareset,
+	devinit,
+	vgaattach,
+	devclone,
+	vgawalk,
+	vgastat,
+	vgaopen,
+	devcreate,
+	vgaclose,
+	vgaread,
+	devbread,
+	vgawrite,
+	devbwrite,
+	devremove,
+	devwstat,
+};

@@ 0,0 1,232 @@
+#include	"u.h"
+#include	"../port/lib.h"
+#include	"mem.h"
+#include	"dat.h"
+#include	"fns.h"
+#include	"io.h"
+
+typedef struct DMAport	DMAport;
+typedef struct DMA	DMA;
+typedef struct DMAxfer	DMAxfer;
+
+enum
+{
+	/*
+	 *  the byte registers for DMA0 are all one byte apart
+	 */
+	Dma0=		0x00,
+	Dma0status=	Dma0+0x8,	/* status port */
+	Dma0reset=	Dma0+0xD,	/* reset port */
+
+	/*
+	 *  the byte registers for DMA1 are all two bytes apart (why?)
+	 */
+	Dma1=		0xC0,
+	Dma1status=	Dma1+2*0x8,	/* status port */
+	Dma1reset=	Dma1+2*0xD,	/* reset port */
+};
+
+/*
+ *  state of a dma transfer
+ */
+struct DMAxfer
+{
+	ulong	bpa;		/* bounce buffer physical address */
+	void*	bva;		/* bounce buffer virtual address */
+	void*	va;		/* virtual address destination/src */
+	long	len;		/* bytes to be transferred */
+	int	isread;
+};
+
+/*
+ *  the dma controllers.  the first half of this structure specifies
+ *  the I/O ports used by the DMA controllers.
+ */
+struct DMAport
+{
+	uchar	addr[4];	/* current address (4 channels) */
+	uchar	count[4];	/* current count (4 channels) */
+	uchar	page[4];	/* page registers (4 channels) */
+	uchar	cmd;		/* command status register */
+	uchar	req;		/* request registers */
+	uchar	sbm;		/* single bit mask register */
+	uchar	mode;		/* mode register */
+	uchar	cbp;		/* clear byte pointer */
+	uchar	mc;		/* master clear */
+	uchar	cmask;		/* clear mask register */
+	uchar	wam;		/* write all mask register bit */
+};
+
+struct DMA
+{
+	DMAport;
+	int	shift;
+	Lock;
+	DMAxfer	x[4];
+};
+
+DMA dma[2] = {
+	{ 0x00, 0x02, 0x04, 0x06,
+	  0x01, 0x03, 0x05, 0x07,
+	  0x87, 0x83, 0x81, 0x82,
+	  0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+	 0 },
+
+	{ 0xc0, 0xc4, 0xc8, 0xcc,
+	  0xc2, 0xc6, 0xca, 0xce,
+	  0x8f, 0x8b, 0x89, 0x8a,
+	  0xd0, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc, 0xde,
+	 1 },
+};
+
+/*
+ *  DMA must be in the first 16MB.  This gets called early by the
+ *  initialisation routines of any devices which require DMA to ensure
+ *  the allocated bounce buffers are below the 16MB limit.
+ */
+void
+dmainit(int chan)
+{
+	DMA *dp;
+	DMAxfer *xp;
+	ulong v;
+
+	dp = &dma[(chan>>2)&1];
+	chan = chan & 3;
+	xp = &dp->x[chan];
+	if(xp->bva != nil)
+		return;
+
+	v = (ulong)xalloc(BY2PG+BY2PG);
+	if(v == 0 || PADDR(v) >= 16*MB){
+		print("dmainit: chan %d: 0x%luX out of range\n", chan, v);
+		xfree((void*)v);
+		v = 0;
+	}
+	xp->bva = (void*)ROUND(v, BY2PG);
+	xp->bpa = PADDR(xp->bva);
+	xp->len = 0;
+	xp->isread = 0;
+}
+
+/*
+ *  setup a dma transfer.  if the destination is not in kernel
+ *  memory, allocate a page for the transfer.
+ *
+ *  we assume BIOS has set up the command register before we
+ *  are booted.
+ *
+ *  return the updated transfer length (we can't transfer across 64k
+ *  boundaries)
+ */
+long
+dmasetup(int chan, void *va, long len, int isread)
+{
+	DMA *dp;
+	ulong pa;
+	uchar mode;
+	DMAxfer *xp;
+
+	dp = &dma[(chan>>2)&1];
+	chan = chan & 3;
+	xp = &dp->x[chan];
+
+	/*
+	 *  if this isn't kernel memory or crossing 64k boundary or above 16 meg
+	 *  use the allocated low memory page.
+	 */
+	pa = PADDR(va);
+	if((((ulong)va)&0xF0000000) != KZERO
+	|| (pa&0xFFFF0000) != ((pa+len)&0xFFFF0000)
+	|| pa >= 16*MB) {
+		if(xp->bva == nil)
+			return -1;
+		if(len > BY2PG)
+			len = BY2PG;
+		if(!isread)
+			memmove(xp->bva, va, len);
+		xp->va = va;
+		xp->len = len;
+		xp->isread = isread;
+		pa = xp->bpa;
+	}
+	else
+		xp->len = 0;
+
+	/*
+	 * this setup must be atomic
+	 */
+	ilock(dp);
+	mode = (isread ? 0x44 : 0x48) | chan;
+	outb(dp->mode, mode);	/* single mode dma (give CPU a chance at mem) */
+	outb(dp->page[chan], pa>>16);
+	outb(dp->cbp, 0);		/* set count & address to their first byte */
+	outb(dp->addr[chan], pa>>dp->shift);		/* set address */
+	outb(dp->addr[chan], pa>>(8+dp->shift));
+	outb(dp->count[chan], (len>>dp->shift)-1);		/* set count */
+	outb(dp->count[chan], ((len>>dp->shift)-1)>>8);
+	outb(dp->sbm, chan);		/* enable the channel */
+	iunlock(dp);
+
+	return len;
+}
+
+int
+dmadone(int chan)
+{
+	DMA *dp;
+
+	dp = &dma[(chan>>2)&1];
+	chan = chan & 3;
+
+	return inb(dp->cmd) & (1<<chan);
+}
+
+/*
+ *  this must be called after a dma has been completed.
+ *
+ *  if a page has been allocated for the dma,
+ *  copy the data into the actual destination
+ *  and free the page.
+ */
+void
+dmaend(int chan)
+{
+	DMA *dp;
+	DMAxfer *xp;
+
+	dp = &dma[(chan>>2)&1];
+	chan = chan & 3;
+
+	/*
+	 *  disable the channel
+	 */
+	ilock(dp);
+	outb(dp->sbm, 4|chan);
+	iunlock(dp);
+
+	xp = &dp->x[chan];
+	if(xp->len == 0 || !xp->isread)
+		return;
+
+	/*
+	 *  copy out of temporary page
+	 */
+	memmove(xp->va, xp->bva, xp->len);
+	xp->len = 0;
+}
+
+/*
+int
+dmacount(int chan)
+{
+	int     retval;
+	DMA     *dp;
+ 
+	dp = &dma[(chan>>2)&1];
+	outb(dp->cbp, 0);
+	retval = inb(dp->count[chan]);
+	retval |= inb(dp->count[chan]) << 8;
+	return((retval<<dp->shift)+1);
+}
+ */

@@ 0,0 1,33 @@
+enum {
+	MaxEther	= 24,
+	Ntypes		= 8,
+};
+
+typedef struct Ether Ether;
+struct Ether {
+	ISAConf;			/* hardware info */
+
+	int	ctlrno;
+	int	tbdf;			/* type+busno+devno+funcno */
+	int	mbps;			/* Mbps */
+	uchar	ea[Eaddrlen];
+
+	void	(*attach)(Ether*);	/* filled in by reset routine */
+	void	(*transmit)(Ether*);
+	void	(*interrupt)(Ureg*, void*);
+	long	(*ifstat)(Ether*, void*, long, ulong);
+	void	*ctlr;
+
+	Queue*	oq;
+
+	Netif;
+};
+
+extern Block* etheriq(Ether*, Block*, int);
+extern void addethercard(char*, int(*)(Ether*));
+extern ulong ethercrc(uchar*, int);
+
+#define NEXT(x, l)	(((x)+1)%(l))
+#define PREV(x, l)	(((x) == 0) ? (l)-1: (x)-1)
+#define	HOWMANY(x, y)	(((x)+((y)-1))/(y))
+#define ROUNDUP(x, y)	(HOWMANY((x), (y))*(y))

@@ 0,0 1,63 @@
+#include	"u.h"
+#include	"../port/lib.h"
+#include	"mem.h"
+#include	"dat.h"
+#include	"fns.h"
+#include	"ureg.h"
+#include	"../port/error.h"
+
+/*
+ *  find out fault address and type of access.
+ *  Call common fault handler.
+ */
+void
+faultalpha(Ureg *ur)
+{
+	ulong addr, cause;
+	int read, user;
+	char buf[ERRLEN];
+	uvlong x;
+
+	x = ur->a0&0xffffffff80000000LL;
+	if (x != 0LL && x != 0xffffffff80000000LL)
+		iprint("faultalpha bad addr %llux pc %llux\n", ur->a0, ur->pc);
+
+	addr = (ulong)ur->a0;
+	cause = (ulong)ur->a2;
+	addr &= ~(BY2PG-1);
+	read = (cause !=1);
+	user = (ulong)ur->status&UMODE;
+
+/*	print("fault %s pc=0x%lux addr=0x%lux 0x%lux\n",
+		read? (cause != 0) ? "ifetch" : "read" : "write", (ulong)ur->pc, addr, (ulong)ur->a1); /**/
+
+	if(fault(addr, read) == 0)
+		return;
+
+	if(user){
+		sprint(buf, "sys: trap: fault %s addr=0x%lux",
+			read? (cause != 0) ? "ifetch" : "read" : "write", (ulong)ur->a0);
+		postnote(up, 1, buf, NDebug);
+		return;
+	}
+
+	iprint("kernel %s vaddr=0x%lux\n", read? (cause != 0) ? "ifetch" : "read" : "write", (ulong)ur->a0);
+iprint("ptbr %lux up %lux\n", (ulong)m->ptbr, up);
+if(up) iprint("top %lux lvl2 %lux\n", up->mmutop->va, up->mmulvl2->va);
+if(up) iprint("top[N-1] %lux\n", ((uvlong *)up->mmutop->va)[PTE2PG-1]);
+	iprint("st=0x%lux pc=0x%lux sp=0x%lux\n", (ulong)ur->status, (ulong)ur->pc, (ulong)ur->sp);
+	dumpregs(ur);
+	panic("fault");
+}
+
+/*
+ * called in sysfile.c
+ */
+void
+evenaddr(ulong addr)
+{
+	if(addr & 3){
+		postnote(up, 1, "sys: odd address", NDebug);
+		error(Ebadarg);
+	}
+}

@@ 0,0 1,173 @@
+typedef	struct FController FController;
+typedef	struct FDrive FDrive;
+typedef struct FType FType;
+
+static void floppyintr(Ureg*);
+static void floppyon(FDrive*);
+static void floppyoff(FDrive*);
+static void floppysetdef(FDrive*);
+
+/*
+ *  a floppy drive
+ */
+struct FDrive
+{
+	FType	*t;		/* floppy type */
+	int	dt;		/* drive type */
+	int	dev;
+
+	ulong	lasttouched;	/* time last touched */
+	int	cyl;		/* current arm position */
+	int	confused;	/* needs to be recalibrated */
+	int	vers;
+
+	int	tcyl;		/* target cylinder */
+	int	thead;		/* target head */
+	int	tsec;		/* target sector */
+	long	len;		/* size of xfer */
+
+	uchar	*cache;		/* track cache */
+	int	ccyl;
+	int	chead;
+
+	Rendez	r;		/* waiting here for motor to spin up */
+};
+
+/*
+ *  controller for 4 floppys
+ */
+struct FController
+{
+	QLock;			/* exclusive access to the contoller */
+
+	int	ndrive;
+	FDrive	*d;		/* the floppy drives */
+	FDrive	*selected;
+	int	rate;		/* current rate selected */
+	uchar	cmd[14];	/* command */
+	int	ncmd;		/* # command bytes */
+	uchar	stat[14];	/* command status */
+	int	nstat;		/* # status bytes */
+	int	confused;	/* controler needs to be reset */
+	Rendez	r;		/* wait here for command termination */
+	int	motor;		/* bit mask of spinning disks */
+	Rendez	kr;		/* for motor watcher */
+};
+
+/*
+ *  floppy types (all MFM encoding)
+ */
+struct FType
+{
+	char	*name;
+	int	dt;		/* compatible drive type */
+	int	bytes;		/* bytes/sector */
+	int	sectors;	/* sectors/track */
+	int	heads;		/* number of heads */
+	int	steps;		/* steps per cylinder */
+	int	tracks;		/* tracks/disk */
+	int	gpl;		/* intersector gap length for read/write */	
+	int	fgpl;		/* intersector gap length for format */
+	int	rate;		/* rate code */
+
+	/*
+	 *  these depend on previous entries and are set filled in
+	 *  by floppyinit
+	 */
+	int	bcode;		/* coded version of bytes for the controller */
+	long	cap;		/* drive capacity in bytes */
+	long	tsize;		/* track size in bytes */
+};
+/* bits in the registers */
+enum
+{
+	/* status registers a & b */
+	Psra=		0x3f0,
+	Psrb=		0x3f1,
+
+	/* digital output register */
+	Pdor=		0x3f2,
+	Fintena=	0x8,	/* enable floppy interrupt */
+	Fena=		0x4,	/* 0 == reset controller */
+
+	/* main status register */
+	Pmsr=		0x3f4,
+	Fready=		0x80,	/* ready to be touched */
+	Ffrom=		0x40,	/* data from controller */
+	Ffloppybusy=	0x10,	/* operation not over */
+
+	/* data register */
+	Pfdata=		0x3f5,
+	Frecal=		0x07,	/* recalibrate cmd */
+	Fseek=		0x0f,	/* seek cmd */
+	Fsense=		0x08,	/* sense cmd */
+	Fread=		0x66,	/* read cmd */
+	Freadid=	0x4a,	/* read track id */
+	Fspec=		0x03,	/* set hold times */
+	Fwrite=		0x45,	/* write cmd */
+	Fformat=	0x4d,	/* format cmd */
+	Fmulti=		0x80,	/* or'd with Fread or Fwrite for multi-head */
+	Fdumpreg=	0x0e,	/* dump internal registers */
+
+	/* digital input register */
+	Pdir=		0x3F7,	/* disk changed port (read only) */
+	Pdsr=		0x3F7,	/* data rate select port (write only) */
+	Fchange=	0x80,	/* disk has changed */
+
+	/* status 0 byte */
+	Drivemask=	3<<0,
+	Seekend=	1<<5,
+	Codemask=	(3<<6)|(3<<3),
+	Cmdexec=	1<<6,
+
+	/* status 1 byte */
+	Overrun=	0x10,
+};
+
+
+static void
+pcfloppyintr(Ureg *ur, void *a)
+{
+	USED(a);
+
+	floppyintr(ur);
+}
+
+void
+floppysetup0(FController *fl)
+{
+	fl->ndrive = 1;
+}
+
+void
+floppysetup1(FController *fl)
+{
+	if(fl->ndrive > 0){
+		fl->d[0].dt = 4;
+		floppysetdef(&fl->d[0]);
+	}
+	if(fl->ndrive > 1){
+		fl->d[1].dt = 4;
+		floppysetdef(&fl->d[1]);
+	}
+
+	intrenable(VectorPIC+IrqFLOPPY, pcfloppyintr, fl, BUSUNKNOWN);
+}
+
+/*
+ *  eject disk
+ */
+void
+floppyeject(FDrive *dp)
+{
+	floppyon(dp);
+	dp->vers++;
+	floppyoff(dp);
+}
+
+int 
+floppyexec(char *a, long b, int c)
+{
+	USED(a, b, c);
+	return b;
+}

@@ 0,0 1,108 @@
+#include "../port/portfns.h"
+
+void		addclock0link(void (*)(void));
+void		archinit(void);
+void		arginit(void);
+void		arith(void);
+void		clearmmucache(void);
+void		clock(Ureg*);
+void		clockinit(void);
+#define 	coherence 	mb
+int		cistrcmp(char*, char*);
+int		cistrncmp(char*, char*, int);
+void		cpuidprint(void);
+void		cserve(ulong, ulong);
+int	dmacount(int);
+int	dmadone(int);
+void	dmaend(int);
+void	dmainit(int);
+long	dmasetup(int, void*, long, int);
+void		evenaddr(ulong);
+void		fataltrap(Ureg *, char *);
+void		fault0(void);
+void		faultalpha(Ureg*);
+ulong	fcr31(void);
+void		firmware(void);
+#define	flushpage(s)	icflush()
+void		fpenab(int);
+void		fptrap(Ureg*);
+ulong	getcallerpc(void*);
+char		*getconf(char*);
+ulong	getfcr(void);
+ulong	getstatus(void);
+void		gotopc(ulong);
+int		i8042auxcmd(int);
+void		i8042auxenable(void (*)(int, int));
+void		i8042reset(void);
+void		i8259init(void);
+int		i8259enable(int, int, Irqctl*);
+#define	idlehands()			/* nothing to do in the runproc */
+void		icflush(void);
+void		illegal0(void);
+void		intr(Ureg*);
+void		intr0(void);
+void		intrenable(int, void (*)(Ureg*, void*), void*, int);
+int		iprint(char*, ...);
+int		isaconfig(char*, int, ISAConf*);
+void		kbdinit(void);
+void		*kmapv(uvlong, int);
+int		kprint(char*, ...);
+void		launchinit(void);
+void		launch(int);
+void		links(void);
+void		mb(void);
+ulong 	meminit(void);
+void		mmuinit(void);
+#define	mmunewpage(x)
+void		mntdump(void);
+void		ns16552special(int, int, Queue**, Queue**, int (*)(Queue*, int));
+void		ns16552setup(ulong, ulong, char*);
+void		ns16552install(void);
+void		ns16552intr(int);
+ulong	pcibarsize(Pcidev*, int);
+int	pcicfgr8(Pcidev*, int);
+int	pcicfgr16(Pcidev*, int);
+int	pcicfgr32(Pcidev*, int);
+void	pcicfgw8(Pcidev*, int, int);
+void	pcicfgw16(Pcidev*, int, int);
+void	pcicfgw32(Pcidev*, int, int);
+void	pcihinv(Pcidev*);
+Pcidev* pcimatch(Pcidev*, int, int);
+void	pcireset(void);
+void		prflush(void);
+void		printinit(void);
+#define	procrestore(p)
+#define	procsave(p)
+#define	procsetup(p)	((p)->fpstate = FPinit)
+void		restfpregs(FPsave*);
+void		screeninit(void);
+void		(*screenputs)(char*, int);
+void 		setpcb(PCB *);
+PCB		*swpctx(PCB *);
+void		syscall0(void);
+int		tas(ulong*);
+void		tlbflush(int, ulong);
+void		touser(void*);
+void		trapinit(void);
+void		unaligned(void);
+void		wrent(int, void*);
+void		wrvptptr(uvlong);
+
+#define	waserror()	(up->nerrlab++, setlabel(&up->errlab[up->nerrlab-1]))
+#define	kmapperm(x)	kmap(x)
+#define KADDR(a)	((void*)((ulong)(a)|KZERO))
+#define PADDR(a)	((ulong)(a)&~KZERO)
+
+#define	inb(p)	(arch->_inb)(p)
+#define	ins(p)	(arch->_ins)(p)
+#define	inl(p)	(arch->_inl)(p)
+#define	outb(p, x)	(arch->_outb)((p), (x))
+#define	outs(p, x)	(arch->_outs)((p), (x))
+#define	outl(p, x)	(arch->_outl)((p), (x))
+
+#define	insb(p, buf, len)	(arch->_insb)((p), (buf), (len))
+#define	inss(p, buf, len)		(arch->_inss)((p), (buf), (len))
+#define	insl(p, buf, len)		(arch->_insl)((p), (buf), (len))
+#define	outsb(p, buf, len)	(arch->_outsb)((p), (buf), (len))
+#define	outss(p, buf, len)	(arch->_outss)((p), (buf), (len))
+#define	outsl(p, buf, len)	(arch->_outsl)((p), (buf), (len))

@@ 0,0 1,46 @@
+#include	"u.h"
+#include	"../port/lib.h"
+#include	"mem.h"
+#include	"dat.h"
+#include	"fns.h"
+#include	"ureg.h"
+#include	"io.h"
+#include	"../port/error.h"
+
+char *fpcause[] =
+{
+	"invalid operation",
+	"division by zero",
+	"overflow",
+	"underflow",
+	"inexact operation",
+	"integer overflow",
+};
+char	*fpexcname(Ureg*, ulong, char*);
+
+void
+fptrap(Ureg *ur)
+{
+	char buf[ERRLEN];
+	int i;
+	ulong reason;
+
+	ur->pc &= ~2;
+	reason = (ulong)ur->a0;
+	for (i = 1; i < 6; i++)
+		if (reason & (1<<i)) {
+			sprint(buf, "fp: %s", fpcause[i-1]);
+			goto found;
+		}
+	sprint(buf, "fp: code 0x%lux", reason);
+
+found:
+	fataltrap(ur, buf);
+}
+
+char*
+fpexcname(Ureg *ur, ulong fcr31, char *buf)
+{
+	USED(ur, fcr31, buf);
+	return buf;
+}

@@ 0,0 1,151 @@
+#include "u.h"
+#include "../port/lib.h"
+#include "mem.h"
+#include "dat.h"
+#include "fns.h"
+#include "io.h"
+
+/*
+ *  8259 interrupt controllers
+ */
+enum
+{
+	Int0ctl=	0x20,		/* control port (ICW1, OCW2, OCW3) */
+	Int0aux=	0x21,		/* everything else (ICW2, ICW3, ICW4, OCW1) */
+	Int1ctl=	0xA0,		/* control port */
+	Int1aux=	0xA1,		/* everything else (ICW2, ICW3, ICW4, OCW1) */
+
+	Icw1=		0x10,		/* select bit in ctl register */
+	Ocw2=		0x00,
+	Ocw3=		0x08,
+
+	EOI=		0x20,		/* non-specific end of interrupt */
+
+	Elcr1=		0x4D0,		/* Edge/Level Triggered Register */
+	Elcr2=		0x4D1,
+};
+
+static int int0mask;			/* interrupts enabled for first 8259 */
+static int int1mask;			/* interrupts enabled for second 8259 */
+
+int elcr;				/* mask of level-triggered interrupts */
+
+void
+i8259init(void)
+{
+	int /*elcr1, */ x;
+
+	int0mask = 0xFF;
+	int1mask = 0xFF;
+
+	/*
+	 *  Set up the first 8259 interrupt processor.
+	 *  Make 8259 interrupts start at CPU vector Int0vec.
+	 *  Set the 8259 as master with edge triggered
+	 *  input with fully nested interrupts.
+	 */
+	outb(Int0ctl, (1<<4)|(0<<3)|(1<<0));	/* ICW1 - master, edge triggered,
+					  	   ICW4 will be sent */
+	outb(Int0aux, VectorPIC);		/* ICW2 - interrupt vector offset */
+	outb(Int0aux, 0x04);			/* ICW3 - have slave on level 2 */
+	outb(Int0aux, 0x01);			/* ICW4 - 8086 mode, not buffered */
+
+	/*
+	 *  Set up the second 8259 interrupt processor.
+	 *  Make 8259 interrupts start at CPU vector VectorPIC+8.
+	 *  Set the 8259 as slave with edge triggered
+	 *  input with fully nested interrupts.
+	 */
+	outb(Int1ctl, (1<<4)|(0<<3)|(1<<0));	/* ICW1 - master, edge triggered,
+					  	   ICW4 will be sent */
+	outb(Int1aux, VectorPIC+8);		/* ICW2 - interrupt vector offset */
+	outb(Int1aux, 0x02);			/* ICW3 - I am a slave on level 2 */
+	outb(Int1aux, 0x01);			/* ICW4 - 8086 mode, not buffered */
+	outb(Int1aux, int1mask);
+
+	/*
+	 *  pass #2 8259 interrupts to #1
+	 */
+	int0mask &= ~0x04;
+	outb(Int0aux, int0mask);
+
+	/*
+	 * Set Ocw3 to return the ISR when ctl read.
+	 * After initialisation status read is set to IRR.
+	 * Read IRR first to possibly deassert an outstanding
+	 * interrupt.
+	 */
+	x = inb(Int0ctl); USED(x);
+	outb(Int0ctl, Ocw3|0x03);
+	x = inb(Int1ctl); USED(x);
+	outb(Int1ctl, Ocw3|0x03);
+
+	/*
+	 * Check for Edge/Level register.
+	 * This check may not work for all chipsets.
+	 */
+/*	elcr1 = inb(Elcr1);
+	outb(Elcr1, 0);
+	if(inb(Elcr1) == 0){
+		outb(Elcr1, 0x20);
+		if(inb(Elcr1) == 0x20)
+			elcr = (inb(Elcr2)<<8)|elcr1;
+	}
+	outb(Elcr1, elcr1);
+	if(elcr)
+		iprint("ELCR: %4.4uX\n", elcr);
+/**/
+}
+
+int
+i8259isr(int v)
+{
+	int isr;
+
+	/*
+	 *  tell the 8259 that we're done with the
+	 *  highest level interrupt (interrupts are still
+	 *  off at this point)
+	 */
+	isr = 0;
+	if(v >= VectorPIC && v <= MaxVectorPIC){
+		isr = inb(Int0ctl);
+		outb(Int0ctl, EOI);
+		if(v >= VectorPIC+8){
+			isr |= inb(Int1ctl)<<8;
+			outb(Int1ctl, EOI);
+		}
+	}
+
+	return isr & (1<<(v-VectorPIC));
+}
+
+int
+i8259enable(int v, int, Irqctl* irqctl)
+{
+	if(v < VectorPIC || v > MaxVectorPIC){
+		iprint("i8259enable: vector %d out of range\n", v);
+		return -1;
+	}
+	v -= VectorPIC;
+
+	/*
+	 *  enable corresponding interrupt in 8259
+	 */
+	if(v < 8){
+		int0mask &= ~(1<<v);
+		outb(Int0aux, int0mask);
+	}
+	else{
+		int1mask &= ~(1<<(v-8));
+		outb(Int1aux, int1mask);
+	}
+
+	if(elcr & (1<<v))
+		irqctl->eoi = i8259isr;
+	else
+		irqctl->isr = i8259isr;
+	irqctl->isintr = 1;
+
+	return v;
+}

@@ 0,0 1,204 @@
+enum {
+	Uart0		= 0x3F8,
+	Uart1		= 0x2F8,
+	  UartFREQ	= 1843200,
+};
+
+enum {
+/*	VectorPIC	= 32,		/* external i8259 interrupts */
+	IrqCLOCK	= 0,
+	IrqKBD		= 1,
+	IrqUART1	= 3,
+	IrqUART0	= 4,
+	IrqPCMCIA	= 5,
+	IrqFLOPPY	= 6,
+	IrqLPT		= 7,
+	IrqIRQ7		= 7,
+	IrqAUX		= 12,		/* PS/2 port */
+	IrqIRQ13	= 13,		/* coprocessor on 386 */
+	IrqATA0		= 14,
+	MaxIrqPIC	= 15,
+
+/* deprecated: */
+	VectorPIC	= 128,		/* external [A]PIC interrupts */
+	VectorCLOCK	= VectorPIC+0,
+	VectorKBD	= VectorPIC+1,
+	VectorUART1	= VectorPIC+3,
+	VectorUART0	= VectorPIC+4,
+	VectorPCMCIA	= VectorPIC+5,
+	VectorFLOPPY	= VectorPIC+6,
+	VectorLPT	= VectorPIC+7,
+	VectorIRQ7	= VectorPIC+7,
+	VectorAUX	= VectorPIC+12,	/* PS/2 port */
+	VectorIRQ13	= VectorPIC+13,	/* corocessor on x386 */
+	VectorATA0	= VectorPIC+14,
+	MaxVectorPIC	= VectorPIC+15,
+	VectorPCI	= 16,		/* PCI bus (PLD) */
+};
+
+typedef struct Irq {
+	void	(*f)(Ureg*, void*);	/* handler to call */
+	void*	a;			/* argument to call it with */
+
+	Irq*	next;			/* link to next handler */
+} Irq;
+
+typedef struct Irqctl {
+	int	(*isr)(int);		/* get isr bit for this irq */
+	int	(*eoi)(int);		/* eoi */
+	int	isintr;
+
+	Irq*	irq;			/* handlers on this IRQ */
+} Irqctl;
+
+enum {
+	BusCBUS		= 0,		/* Corollary CBUS */
+	BusCBUSII,			/* Corollary CBUS II */
+	BusEISA,			/* Extended ISA */
+	BusFUTURE,			/* IEEE Futurebus */
+	BusINTERN,			/* Internal bus */
+	BusISA,				/* Industry Standard Architecture */
+	BusMBI,				/* Multibus I */
+	BusMBII,			/* Multibus II */
+	BusMCA,				/* Micro Channel Architecture */
+	BusMPI,				/* MPI */
+	BusMPSA,			/* MPSA */
+	BusNUBUS,			/* Apple Macintosh NuBus */
+	BusPCI,				/* Peripheral Component Interconnect */
+	BusPCMCIA,			/* PC Memory Card International Association */
+	BusTC,				/* DEC TurboChannel */
+	BusVL,				/* VESA Local bus */
+	BusVME,				/* VMEbus */
+	BusXPRESS,			/* Express System Bus */
+};
+
+#define MKBUS(t,b,d,f)	(((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
+#define BUSFNO(tbdf)	(((tbdf)>>8)&0x07)
+#define BUSDNO(tbdf)	(((tbdf)>>11)&0x1F)
+#define BUSBNO(tbdf)	(((tbdf)>>16)&0xFF)
+#define BUSTYPE(tbdf)	((tbdf)>>24)
+#define BUSDF(tbdf)		((tbdf)&0x000FF00)
+#define BUSBDF(tbdf)	((tbdf)&0x0FFFF00)
+#define BUSUNKNOWN	(-1)
+
+enum {
+	MaxEISA		= 16,
+	EISAconfig	= 0xC80,
+};
+
+/*
+ * PCI support code.
+ */
+enum {					/* type 0 and type 1 pre-defined header */
+	PciVID		= 0x00,		/* vendor ID */
+	PciDID		= 0x02,		/* device ID */
+	PciPCR		= 0x04,		/* command */
+	PciPSR		= 0x06,		/* status */
+	PciRID		= 0x08,		/* revision ID */
+	PciCCRp		= 0x09,		/* programming interface class code */
+	PciCCRu		= 0x0A,		/* sub-class code */
+	PciCCRb		= 0x0B,		/* base class code */
+	PciCLS		= 0x0C,		/* cache line size */
+	PciLTR		= 0x0D,		/* latency timer */
+	PciHDT		= 0x0E,		/* header type */
+	PciBST		= 0x0F,		/* BIST */
+
+	PciBAR0		= 0x10,		/* base address */
+	PciBAR1		= 0x14,
+
+	PciINTL		= 0x3C,		/* interrupt line */
+	PciINTP		= 0x3D,		/* interrupt pin */
+};
+
+enum {					/* type 0 pre-defined header */
+	PciBAR2		= 0x18,
+	PciBAR3		= 0x1C,
+	PciBAR4		= 0x20,
+	PciBAR5		= 0x24,
+	PciCIS		= 0x28,		/* cardbus CIS pointer */
+	PciSVID		= 0x2C,		/* subsystem vendor ID */
+	PciSID		= 0x2E,		/* cardbus CIS pointer */
+	PciEBAR0	= 0x30,		/* xpansion ROM base address */
+	PciMGNT		= 0x3E,		/* burst period length */
+	PciMLT		= 0x3F,		/* maximum latency between bursts */
+};
+
+enum {					/* type 1 pre-defined header */
+	PciPBN		= 0x18,		/* primary bus number */
+	PciSBN		= 0x19,		/* secondary bus number */
+	PciUBN		= 0x1A,		/* subordinate bus number */
+	PciSLTR		= 0x1B,		/* secondary latency timer */
+	PciIBR		= 0x1C,		/* I/O base */
+	PciILR		= 0x1D,		/* I/O limit */
+	PciSPSR		= 0x1E,		/* secondary status */
+	PciMBR		= 0x20,		/* memory base */
+	PciMLR		= 0x22,		/* memory limit */
+	PciPMBR		= 0x24,		/* prefetchable memory base */
+	PciPMLR		= 0x26,		/* prefetchable memory limit */
+	PciPUBR		= 0x28,		/* prefetchable base upper 32 bits */
+	PciPULR		= 0x2C,		/* prefetchable limit upper 32 bits */
+	PciIUBR		= 0x30,		/* I/O base upper 16 bits */
+	PciIULR		= 0x32,		/* I/O limit upper 16 bits */
+	PciEBAR1	= 0x28,		/* expansion ROM base address */
+	PciBCR		= 0x3E,		/* bridge control register */
+};
+
+typedef struct Pcidev Pcidev;
+typedef struct Pcidev {
+	int	tbdf;		/* type+bus+device+function */
+	ushort	vid;			/* vendor ID */
+	ushort	did;			/* device ID */
+
+	struct {
+		ulong	bar;		/* base address */
+		int	size;
+	} mem[3];
+
+	uchar	intl;			/* interrupt line */
+	ushort	ccru;
+
+
+	Pcidev*	list;
+	Pcidev*	bridge;			/* down a bus */
+	Pcidev*	link;			/* next device on this bno */
+};
+
+/*
+ * PCMCIA support code.
+ */
+/*
+ * Map between ISA memory space and PCMCIA card memory space.
+ */
+struct PCMmap {
+	ulong	ca;			/* card address */
+	ulong	cea;			/* card end address */
+	ulong	isa;			/* ISA address */
+	int	len;			/* length of the ISA area */
+	int	attr;			/* attribute memory */
+	int	ref;
+};
+
+/*
+ *  SCSI bus
+ */
+enum {
+	MaxScsi		= 8,
+	NTarget		= 8,		/* should be 16... */
+};
+struct Target {
+	int	ctlrno;
+	int	target;
+	uchar*	inq;
+	uchar*	scratch;
+
+	Rendez	rendez;
+
+	int	ok;
+};
+
+typedef int (*Scsiio)(Target*, int, uchar*, int, void*, int*);
+
+typedef struct SCSIdev {
+	char*	type;
+	Scsiio	(*reset)(int, ISAConf*);
+} SCSIdev;

@@ 0,0 1,417 @@
+#include	"u.h"
+#include	"../port/lib.h"
+#include	"mem.h"
+#include	"dat.h"
+#include	"fns.h"
+#include	"io.h"
+#include	"../port/error.h"
+
+enum {
+	Data=		0x60,		/* data port */
+
+	Status=		0x64,		/* status port */
+	 Inready=	0x01,		/*  input character ready */
+	 Outbusy=	0x02,		/*  output busy */
+	 Sysflag=	0x04,		/*  system flag */
+	 Cmddata=	0x08,		/*  cmd==0, data==1 */
+	 Inhibit=	0x10,		/*  keyboard/mouse inhibited */
+	 Minready=	0x20,		/*  mouse character ready */
+	 Rtimeout=	0x40,		/*  general timeout */
+	 Parity=	0x80,
+
+	Cmd=		0x64,		/* command port (write only) */
+
+	Spec=		0x80,
+
+	PF=		Spec|0x20,	/* num pad function key */
+	View=		Spec|0x00,	/* view (shift window up) */
+	KF=		Spec|0x40,	/* function key */
+	Shift=		Spec|0x60,
+	Break=		Spec|0x61,
+	Ctrl=		Spec|0x62,
+	Latin=		Spec|0x63,
+	Caps=		Spec|0x64,
+	Num=		Spec|0x65,
+	Middle=		Spec|0x66,
+	No=		0x00,		/* peter */
+
+	Home=		KF|13,
+	Up=		KF|14,
+	Pgup=		KF|15,
+	Print=		KF|16,
+	Left=		View,
+	Right=		View,
+	End=		'\r',
+	Down=		View,
+	Pgdown=		View,
+	Ins=		KF|20,
+	Del=		0x7F,
+};
+
+uchar kbtab[] = 
+{
+[0x00]	No,	0x1b,	'1',	'2',	'3',	'4',	'5',	'6',
+[0x08]	'7',	'8',	'9',	'0',	'-',	'=',	'\b',	'\t',
+[0x10]	'q',	'w',	'e',	'r',	't',	'y',	'u',	'i',
+[0x18]	'o',	'p',	'[',	']',	'\n',	Ctrl,	'a',	's',
+[0x20]	'd',	'f',	'g',	'h',	'j',	'k',	'l',	';',
+[0x28]	'\'',	'`',	Shift,	'\\',	'z',	'x',	'c',	'v',
+[0x30]	'b',	'n',	'm',	',',	'.',	'/',	Shift,	'*',
+[0x38]	Latin,	' ',	Ctrl,	KF|1,	KF|2,	KF|3,	KF|4,	KF|5,
+[0x40]	KF|6,	KF|7,	KF|8,	KF|9,	KF|10,	Num,	KF|12,	'7',
+[0x48]	'8',	'9',	'-',	'4',	'5',	'6',	'+',	'1',
+[0x50]	'2',	'3',	'0',	'.',	No,	No,	No,	KF|11,
+[0x58]	KF|12,	No,	No,	No,	No,	No,	No,	No,
+};
+
+uchar kbtabshift[] =
+{
+[0x00]	No,	0x1b,	'!',	'@',	'#',	'$',	'%',	'^',
+[0x08]	'&',	'*',	'(',	')',	'_',	'+',	'\b',	'\t',
+[0x10]	'Q',	'W',	'E',	'R',	'T',	'Y',	'U',	'I',
+[0x18]	'O',	'P',	'{',	'}',	'\n',	Ctrl,	'A',	'S',
+[0x20]	'D',	'F',	'G',	'H',	'J',	'K',	'L',	':',
+[0x28]	'"',	'~',	Shift,	'|',	'Z',	'X',	'C',	'V',
+[0x30]	'B',	'N',	'M',	'<',	'>',	'?',	Shift,	'*',
+[0x38]	Latin,	' ',	Ctrl,	KF|1,	KF|2,	KF|3,	KF|4,	KF|5,
+[0x40]	KF|6,	KF|7,	KF|8,	KF|9,	KF|10,	Num,	KF|12,	'7',
+[0x48]	'8',	'9',	'-',	'4',	'5',	'6',	'+',	'1',
+[0x50]	'2',	'3',	'0',	'.',	No,	No,	No,	KF|11,
+[0x58]	KF|12,	No,	No,	No,	No,	No,	No,	No,
+};
+
+uchar kbtabesc1[] =
+{
+[0x00]	No,	No,	No,	No,	No,	No,	No,	No,
+[0x08]	No,	No,	No,	No,	No,	No,	No,	No,
+[0x10]	No,	No,	No,	No,	No,	No,	No,	No,
+[0x18]	No,	No,	No,	No,	'\n',	Ctrl,	No,	No,
+[0x20]	No,	No,	No,	No,	No,	No,	No,	No,
+[0x28]	No,	No,	Shift,	No,	No,	No,	No,	No,
+[0x30]	No,	No,	No,	No,	No,	'/',	No,	Print,
+[0x38]	Latin,	No,	No,	No,	No,	No,	No,	No,
+[0x40]	No,	No,	No,	No,	No,	No,	Break,	Home,
+[0x48]	Up,	Pgup,	No,	Left,	No,	Right,	No,	End,
+[0x50]	Down,	Pgdown,	Ins,	Del,	No,	No,	No,	No,
+[0x58]	No,	No,	No,	No,	No,	No,	No,	No,
+};
+
+enum
+{
+	/* controller command byte */
+	Cscs1=		(1<<6),		/* scan code set 1 */
+	Cauxdis=	(1<<5),		/* mouse disable */
+	Ckbddis=	(1<<4),		/* kbd disable */
+	Csf=		(1<<2),		/* system flag */
+	Cauxint=	(1<<1),		/* mouse interrupt enable */
+	Ckbdint=	(1<<0),		/* kbd interrupt enable */
+};
+
+static Lock i8042lock;
+static uchar ccc;
+static void (*auxputc)(int, int);
+
+/*
+ *  wait for output no longer busy
+ */
+static int
+outready(void)
+{
+	int tries;
+
+	for(tries = 0; (inb(Status) & Outbusy); tries++){
+		if(tries > 500)
+			return -1;
+		delay(2);
+	}
+	return 0;
+}
+
+/*
+ *  wait for input
+ */
+static int
+inready(void)
+{
+	int tries;
+
+	for(tries = 0; !(inb(Status) & Inready); tries++){
+		if(tries > 500)
+			return -1;
+		delay(2);
+	}
+	return 0;
+}
+
+/*
+ *  ask 8042 to reset the machine
+ */
+void
+i8042reset(void)
+{
+	ushort *s = KADDR(0x472);
+	int i, x;
+
+	*s = 0x1234;		/* BIOS warm-boot flag */
+
+	/*
+	 *  newer reset the machine command
+	 */
+	outready();
+	outb(Cmd, 0xFE);
+	outready();
+
+	/*
+	 *  Pulse it by hand (old somewhat reliable)
+	 */
+	x = 0xDF;
+	for(i = 0; i < 5; i++){
+		x ^= 1;
+		outready();
+		outb(Cmd, 0xD1);
+		outready();
+		outb(Data, x);	/* toggle reset */
+		delay(100);
+	}
+}
+
+int
+i8042auxcmd(int cmd)
+{
+	unsigned int c;
+	int tries;
+
+	c = 0;
+	tries = 0;
+
+	ilock(&i8042lock);
+	do{
+		if(tries++ > 2)
+			break;
+		if(outready() < 0)
+			break;
+		outb(Cmd, 0xD4);
+		if(outready() < 0)
+			break;
+		outb(Data, cmd);
+		if(outready() < 0)
+			break;
+		if(inready() < 0)
+			break;
+		c = inb(Data);
+	} while(c == 0xFE || c == 0);
+	iunlock(&i8042lock);
+
+	if(c != 0xFA){
+		print("i8042: %2.2ux returned to the %2.2ux command\n", c, cmd);
+		return -1;
+	}
+	return 0;
+}
+
+/*
+ *  keyboard interrupt
+ */
+static void
+i8042intr(Ureg*, void*)
+{
+	int s, c, i;
+	static int esc1, esc2;
+	static int alt, caps, ctl, num, shift;
+	static int collecting, nk;
+	static uchar kc[5];
+	int keyup;
+
+	/*
+	 *  get status
+	 */
+	lock(&i8042lock);
+	s = inb(Status);
+	if(!(s&Inready)){
+		unlock(&i8042lock);
+		return;
+	}
+
+	/*
+	 *  get the character
+	 */
+	c = inb(Data);
+	unlock(&i8042lock);
+
+	/*
+	 *  if it's the aux port...
+	 */
+	if(s & Minready){
+		if(auxputc != nil)
+			auxputc(c, shift);
+		return;
+	}
+
+	/*
+	 *  e0's is the first of a 2 character sequence
+	 */
+	if(c == 0xe0){
+		esc1 = 1;
+		return;
+	} else if(c == 0xe1){
+		esc2 = 2;
+		return;
+	}
+
+	keyup = c&0x80;
+	c &= 0x7f;
+	if(c > sizeof kbtab){
+		c |= keyup;
+		if(c != 0xFF)	/* these come fairly often: CAPSLOCK U Y */
+			print("unknown key %ux\n", c);
+		return;
+	}
+
+	if(esc1){
+		c = kbtabesc1[c];
+		esc1 = 0;
+	} else if(esc2){
+		esc2--;
+		return;
+	} else if(shift)
+		c = kbtabshift[c];
+	else
+		c = kbtab[c];
+
+	if(caps && c<='z' && c>='a')
+		c += 'A' - 'a';
+
+	/*
+	 *  keyup only important for shifts
+	 */
+	if(keyup){
+		switch(c){
+		case Latin:
+			alt = 0;
+			break;
+		case Shift:
+			shift = 0;
+			break;
+		case Ctrl:
+			ctl = 0;
+			break;
+		}
+		return;
+	}
+
+	/*
+ 	 *  normal character
+	 */
+	if(!(c & Spec)){
+		if(ctl){
+			if(alt && c == Del)
+				exit(0);
+			c &= 0x1f;
+		}
+		if(!collecting){
+			kbdputc(kbdq, c);
+			return;
+		}
+		kc[nk++] = c;
+		c = latin1(kc, nk);
+		if(c < -1)	/* need more keystrokes */
+			return;
+		if(c != -1)	/* valid sequence */
+			kbdputc(kbdq, c);
+		else	/* dump characters */
+			for(i=0; i<nk; i++)
+				kbdputc(kbdq, kc[i]);
+		nk = 0;
+		collecting = 0;
+		return;
+	} else {
+		switch(c){
+		case Caps:
+			caps ^= 1;
+			return;
+		case Num:
+			num ^= 1;
+			return;
+		case Shift:
+			shift = 1;
+			return;
+		case Latin:
+			alt = 1;
+			collecting = 1;
+			nk = 0;
+			return;
+		case Ctrl:
+			ctl = 1;
+			return;
+		}
+	}
+	kbdputc(kbdq, c);
+}
+
+void
+i8042auxenable(void (*putc)(int, int))
+{
+	char *err = "i8042: aux init failed\n";
+
+	/* enable kbd/aux xfers and interrupts */
+	ccc &= ~Cauxdis;
+	ccc |= Cauxint;
+
+	ilock(&i8042lock);
+	if(outready() < 0)
+		print(err);
+	outb(Cmd, 0x60);			/* write control register */
+	if(outready() < 0)
+		print(err);
+	outb(Data, ccc);
+	if(outready() < 0)
+		print(err);
+	outb(Cmd, 0xA8);			/* auxilliary device enable */
+	if(outready() < 0){
+		iunlock(&i8042lock);
+		return;
+	}
+	auxputc = putc;
+	intrenable(VectorAUX, i8042intr, 0, BUSUNKNOWN);
+	iunlock(&i8042lock);
+}
+
+void
+kbdinit(void)
+{
+	int c, x;
+
+	kbdq = qopen(4*1024, 0, 0, 0);
+	if(kbdq == nil)
+		panic("kbdinit");
+	qnoblock(kbdq, 1);
+
+	intrenable(VectorKBD, i8042intr, 0, BUSUNKNOWN);
+
+	/* wait for a quiescent controller */
+	while((c = inb(Status)) & (Outbusy | Inready))
+		if(c & Inready) {
+			x = inb(Data);
+			USED(x);
+		}
+
+	/* get current controller command byte */
+	outb(Cmd, 0x20);
+	if(inready() < 0){
+		print("kbdinit: can't read ccc\n");
+		ccc = 0;
+	} else
+		ccc = inb(Data);
+
+	/* enable kbd xfers and interrupts */
+	/* disable mouse */
+	ccc &= ~Ckbddis;
+	ccc |= Csf | Ckbdint | Cscs1;
+	if(outready() < 0)
+		print("kbd init failed\n");
+	outb(Cmd, 0x60);
+	if(outready() < 0)
+		print("kbd init failed\n");
+	outb(Data, ccc);
+	outready();
+}