From e53c69c3a72a6c3676a8940a622efe9c20f7dc97 Mon Sep 17 00:00:00 2001 From: David du Colombier <0intro@gmail.com> Date: Sat, 26 Jan 2002 00:00:00 +0000 Subject: [PATCH] Plan 9 from Bell Labs 2002-01-26 --- mtx/clock.c | 6 ++--- mtx/dat.h | 6 +++++ mtx/devrtc.c | 21 +++++++++++++++-- mtx/fns.h | 4 ++-- mtx/l.s | 17 -------------- mtx/main.c | 2 +- mtx/mmu.c | 66 ++++++++++++++++++++++++---------------------------- 7 files changed, 61 insertions(+), 61 deletions(-) diff --git a/mtx/clock.c b/mtx/clock.c index f025ef06f10ec38beab7de2656470753d2dfd2d1..7024198369d12ab042410b1c3b511edf576a5d9d 100644 --- a/mtx/clock.c +++ b/mtx/clock.c @@ -28,16 +28,16 @@ delayloopinit(void) void clockinit(void) { - /* XXX the hardcoding of these values is WRONG */ + /* XXX this should not be hard coded! */ m->cpuhz = 300000000; m->bushz = 66666666; m->dechz = m->bushz/4; /* true for all 604e */ - m->tbhz = m->dechz; /* conjecture; manual says bugger all */ + m->tbhz = m->dechz; /* conjecture; manual doesn't say */ delayloopinit(); - clkreload = m->dechz/HZ-1; /* decremented at 1/4 bus clock speed */ + clkreload = m->dechz/HZ-1; putdec(clkreload); } diff --git a/mtx/dat.h b/mtx/dat.h index 60642cd2e894ffa17978280c469ee003527ebb89..4e9d698bf4fe6811cbcf9b5050f49ab8471bd609 100644 --- a/mtx/dat.h +++ b/mtx/dat.h @@ -152,6 +152,12 @@ struct Mach int intr; int flushmmu; /* make current proc flush it's mmu state */ + ulong ptabbase; /* start of page table in kernel virtual space */ + int slotgen; /* next pte (byte offset) when pteg is full */ + int mmupid; /* next mmu pid to use */ + int minpid; + int maxpid; + ulong spuriousintr; int lastintr; diff --git a/mtx/devrtc.c b/mtx/devrtc.c index bcc640a21afe8cf7280c04a5f014da5381e0572a..5b6a2399cfefd2e874e1be3f7cbb22640d788ab3 100644 --- a/mtx/devrtc.c +++ b/mtx/devrtc.c @@ -21,8 +21,9 @@ enum{ /* * register offsets into time of day clock */ - NVflags= 0x1ff0, - NVctl= 0x1ff8, + NVflags= 0x1ff0, + NVwatchdog= 0x1ff7, + NVctl= 0x1ff8, NVsec, NVmin, NVhour, @@ -37,6 +38,14 @@ enum{ RTsign = (1<<5), RTcal = 0x1f, + /* NVwatchdog */ + WDsteer = (1<<7), /* 0 -> intr, 1 -> reset */ + WDmult = (1<<2), /* 5 bits of multiplier */ + WDres0 = (0<<0), /* 1/16 sec resolution */ + WDres1 = (1<<0), /* 1/4 sec resolution */ + WDres2 = (2<<0), /* 1 sec resolution */ + WDres3 = (3<<0), /* 4 sec resolution */ + Qdir = 0, Qrtc, Qnvram, @@ -244,6 +253,14 @@ nvcksum(void) { } +void +watchreset(void) +{ + splhi(); + nvput(NVwatchdog, WDsteer|(1*WDmult)|WDres0); + for(;;); +} + static int getbcd(int bcd) { diff --git a/mtx/fns.h b/mtx/fns.h index 34f5f34e8b28d32a7903773057df69742ea4b261..0ae7da7346b078757d5c2ddd82c0bc859373b216 100644 --- a/mtx/fns.h +++ b/mtx/fns.h @@ -16,7 +16,6 @@ void delayloopinit(void); void eieio(void); void evenaddr(ulong); void faultpower(Ureg*, ulong addr, int read); -void firmware(void); void fpinit(void); void fprestore(FPsave*); void fpsave(FPsave*); @@ -91,7 +90,7 @@ Pcidev* pcimatch(Pcidev*, int, int); Pcidev* pcimatchtbdf(int); void pcireset(void); void pcisetbme(Pcidev*); -#define procrestore(p) +#define procrestore(p) void procsave(Proc*); void procsetup(Proc*); void putdec(ulong); @@ -114,6 +113,7 @@ void tlbflushall(void); void uartinstall(void); void uartwait(void); /* debugging */ #define userureg(ur) (((ur)->status & MSR_PR) != 0) +void watchreset(void); void wbflush(void); #define waserror() (up->nerrlab++, setlabel(&up->errlab[up->nerrlab-1])) diff --git a/mtx/l.s b/mtx/l.s index 807c34de5f2c9f88d250d80ef7188c6ddc679ad9..4ac687f5a2a95a2552b19c877772d75c522426c0 100644 --- a/mtx/l.s +++ b/mtx/l.s @@ -49,10 +49,6 @@ /* set R2 to correct value */ MOVW $setSB(SB), R2 - /* save SPR(SPRG3), or else we can't go back to firmware! */ - MOVW SPR(SPRG3), R3 - MOVW R3, initsprg3(SB) - /* debugger sets R1 to top of usable memory +1 */ MOVW R1, memsize(SB) @@ -70,7 +66,6 @@ RETURN /* not reached */ GLOBL mach0(SB), $(MAXMACH*BY2PG) -GLOBL initsprg3(SB), $4 GLOBL memsize(SB), $4 /* @@ -285,18 +280,6 @@ tas0: ISYNC RETURN -TEXT firmware(SB), $0 - MOVW initsprg3(SB), R3 - MOVW R3, SPR(SPRG3) -// MOVW $0x4000, R3 -// MOVW R3, SPR(SPRG3) - MOVW R0, SPR(HID0) - MOVW $MSR_IP, R4 - MOVW R4, SPR(SRR1) - MOVW $0xfff00100, R5 - MOVW R5, SPR(SRR0) - RFI - TEXT getpvr(SB), $0 MOVW SPR(PVR), R3 RETURN diff --git a/mtx/main.c b/mtx/main.c index 9772d8c23534069fdaf79e294f8012d52209fc46..f3ac34bfb5cfc0e7731709274339771875c99818 100644 --- a/mtx/main.c +++ b/mtx/main.c @@ -240,7 +240,7 @@ exit(int ispanic) else delay(1000); - firmware(); + watchreset(); } /* diff --git a/mtx/mmu.c b/mtx/mmu.c index 604ea2b6fa8a7219148d50dd7615e97e8696913a..218b7966d272b440d64df20afde7070ec52aa5bc 100644 --- a/mtx/mmu.c +++ b/mtx/mmu.c @@ -14,16 +14,8 @@ * mmu pids, with a background kproc to purge stale pids en mass. */ -static struct { - Lock; - ulong base; /* start of page table in kernel virtual space */ - ulong size; /* number of bytes in page table */ - ulong mask; /* hash mask */ - int slotgen; /* next pte (byte offset) when pteg is full */ - - int pidlock; - int pidgen; /* next mmu pid to use */ -} ptab; +static ulong ptabsize; /* number of bytes in page table */ +static ulong ptabmask; /* hash mask */ /* * VSID is 24 bits. 3 are required to distinguish segments in user @@ -42,20 +34,28 @@ mmuinit(void) { int lhash, mem; extern ulong memsize; /* passed in from ROM monitor */ - - /* heuristically size the hash table */ - lhash = 10; /* log of hash table size */ - mem = (1<<23); - while(mem < memsize) { - lhash++; - mem <<= 1; + ulong v; + + if(ptabsize == 0) { + /* heuristically size the hash table */ + lhash = 10; + mem = (1<<23); + while(mem < memsize) { + lhash++; + mem <<= 1; + } + ptabsize = (1<<(lhash+6)); + ptabmask = (1<ptabbase = (ulong)xspanalloc(ptabsize, 0, ptabsize); + putsdr1(PADDR(m->ptabbase) | (ptabmask>>10)); + m->mmupid = PIDBASE; + + v = getdec(); + memset((void*)m->ptabbase, 0, ptabsize); + v -= getdec(); + print("memset took %lud cycles, dechz %lud\n", v, m->dechz); } void @@ -114,14 +114,13 @@ putmmu(ulong va, ulong pa, Page *pg) panic("putmmu pid"); vsid = VSID(mp, va>>28); - hash = (vsid ^ (va>>12)&0xffff) & ptab.mask; + hash = (vsid ^ (va>>12)&0xffff) & ptabmask; ptehi = PTE0(1, vsid, 0, va); - pteg = ptab.base + BY2PTEG*hash; + pteg = m->ptabbase + BY2PTEG*hash; p = (ulong*)pteg; ep = (ulong*)(pteg+BY2PTEG); q = nil; - ilock(&ptab); tlbflush(va); while(p < ep) { x = p[0]; @@ -135,13 +134,12 @@ if(q[1] == pa) print("putmmu already set pte\n"); p += 2; } if(q == nil) { - q = (ulong*)(pteg+ptab.slotgen); - ptab.slotgen = (ptab.slotgen + BY2PTE) & (BY2PTEG-1); + q = (ulong*)(pteg+m->slotgen); + m->slotgen = (m->slotgen + BY2PTE) & (BY2PTEG-1); } q[0] = ptehi; q[1] = pa; sync(); - iunlock(&ptab); ctl = &pg->cachectl[m->machno]; switch(*ctl) { @@ -164,14 +162,10 @@ newmmupid(void) { int pid; - /* can't use lock() here as we're called from within sched() */ - while(!tas(&ptab.pidlock)) - ; - pid = ptab.pidgen++; - if(pid > PIDMAX) - pid = PIDBASE; - ptab.pidlock = 0; - coherence(); + pid = m->mmupid++; + if(m->mmupid > PIDMAX) + panic("ran out of mmu pids"); +// m->mmupid = PIDBASE; up->mmupid = pid; return pid; }