~kris/9p

9hist

d7e562ed80ef6d34b1648415182f7e4b47938601 — David du Colombier 29 years ago afec380
Plan 9 from Bell Labs 1997-04-05
3 files changed, 58 insertions(+), 29 deletions(-)

M pc/mp.c
M pc/trap.c
M port/devmnt.c
M pc/mp.c => pc/mp.c +33 -28
@@ 187,6 187,9 @@ mpintrinit(Bus* bus, PCMPintr* intr, int vector)
	 */
	v = vector;

	po = intr->flags & PcmpPOMASK;
	el = intr->flags & PcmpELMASK;

	switch(intr->intr){

	default:				/* PcmpINT */


@@ 195,6 198,8 @@ mpintrinit(Bus* bus, PCMPintr* intr, int vector)

	case PcmpNMI:
		v |= ApicNMI;
		po = PcmpHIGH;
		el = PcmpEDGE;
		break;

	case PcmpSMI:


@@ 206,9 211,6 @@ mpintrinit(Bus* bus, PCMPintr* intr, int vector)
		break;
	}

	po = intr->flags & PcmpPOMASK;
	el = intr->flags & PcmpELMASK;

	/*
	 */
	if(bus->type == BusEISA && !po && !el /*&& !(elcr & (1<<(v-VectorPIC)))*/){


@@ 368,7 370,7 @@ mpinit(void)
	PCMP *pcmp;
	ulong *pte;
	uchar *e, *p;
	Apic *apic;
	Apic *apic, *bpapic;
	int clkin;

	i8259init();


@@ 376,7 378,6 @@ mpinit(void)
	if(_mp_ == 0)
		return;
	pcmp = KADDR(_mp_->physaddr);
	clkin = 0;

	/*
	 * Map the local APIC. This should be in the same 4MB segment


@@ 389,6 390,8 @@ mpinit(void)
		mmuflushtlb(PADDR(m->pdb));
	}

	bpapic = 0;

	/*
	 * Run through the table saving information needed for starting application
	 * processors and initialising any I/O APICs. The table is guaranteed to be in


@@ 401,7 404,7 @@ mpinit(void)
	case PcmpPROCESSOR:
		if(apic = mkprocessor((PCMPprocessor*)p)){
			/*
			 * Must initialise the bootstrap processor APIC
			 * Must take a note of bootstrap processor APIC
			 * now as it will be needed in order to start the
			 * application processors later and there's no
			 * guarantee that the bootstrap processor appears


@@ 409,7 412,7 @@ mpinit(void)
			 */
			apic->addr = KADDR(pcmp->lapicbase);
			if(apic->flags & PcmpBP)
				clkin = lapicinit(apic);
				bpapic = apic;
		}
		p += sizeof(PCMPprocessor);
		continue;


@@ 437,31 440,33 @@ mpinit(void)
	}

	/*
	 * Initialise all the processors.
	 * No bootstrap processor, no need to go further.
	 */
	memmove((void*)APBOOTSTRAP, apbootstrap, sizeof(apbootstrap));
	for(apic = mpapic; apic <= &mpapic[MaxAPICNO]; apic++){
		if(!(apic->flags & PcmpEN) || apic->type != PcmpPROCESSOR)
			continue;
	if(bpapic == 0)
		return;

		if(apic->flags & PcmpBP){
			lock(&mprdthilock);
			mprdthi |= (1<<apic->apicno)<<24;
			unlock(&mprdthilock);
	clkin = lapicinit(bpapic);
	lock(&mprdthilock);
	mprdthi |= (1<<bpapic->apicno)<<24;
	unlock(&mprdthilock);

			/*
			 * These interrupts are local to the processor
			 * and do not appear in the I/O APIC so it is OK
			 * to set them now.
			 */
			intrenable(VectorTIMER, clockintr, 0, BUSUNKNOWN);
			intrenable(VectorERROR, lapicerror, 0, BUSUNKNOWN);
			intrenable(VectorSPURIOUS, lapicspurious, 0, BUSUNKNOWN);
			lapiconline(clkin);
			continue;
		}
	/*
	 * These interrupts are local to the processor
	 * and do not appear in the I/O APIC so it is OK
	 * to set them now.
	 */
	intrenable(VectorTIMER, clockintr, 0, BUSUNKNOWN);
	intrenable(VectorERROR, lapicerror, 0, BUSUNKNOWN);
	intrenable(VectorSPURIOUS, lapicspurious, 0, BUSUNKNOWN);
	lapiconline(clkin);

		mpstartap(apic);
	/*
	 * Initialise the application processors.
	 */
	memmove((void*)APBOOTSTRAP, apbootstrap, sizeof(apbootstrap));
	for(apic = mpapic; apic <= &mpapic[MaxAPICNO]; apic++){
		if((apic->flags & (PcmpBP|PcmpEN)) == PcmpEN && apic->type == PcmpPROCESSOR)
			mpstartap(apic);
	}

	/*

M pc/trap.c => pc/trap.c +23 -0
@@ 44,6 44,22 @@ intrenable(int v, void (*f)(Ureg*, void*), void* a, int tbdf)
	unlock(&irqctllock);
}

static void
nmienable(void)
{
	int x;

	/*
	 * Hack: should be locked with NVRAM access.
	 */
	outb(0x70, 0x80);
	outb(0x70, 0);

	x = inb(0x61);
	outb(0x61, 0x08|x);
	outb(0x61, x & ~0x08);
}

void
trapinit(void)
{


@@ 66,6 82,8 @@ trapinit(void)
	intrenable(VectorBPT, debugbpt, 0, BUSUNKNOWN);
	intrenable(VectorPF, fault386, 0, BUSUNKNOWN);
	intrenable(VectorSYSCALL, syscall, 0, BUSUNKNOWN);

	nmienable();
}

char *excname[] = {


@@ 142,6 160,11 @@ trap(Ureg* ureg)
		return;
	}
	else{
		if(v == 2){
			if(m->machno != 0)
				for(;;);
			nmienable();
		}
		dumpregs(ureg);
		if(v < nelem(excname))
			panic("%s", excname[v]);

M port/devmnt.c => port/devmnt.c +2 -1
@@ 639,7 639,8 @@ mountrpc(Mnt *m, Mntrpc *r)
	default:
		if(t == r->request.type+1)
			break;
		print("mnt: mismatch rep 0x%lux T%d R%d rq %d fls %d rp %d\n",
		print("mnt: proc %s %d: mismatch rep 0x%lux T%d R%d rq %d fls %d rp %d\n",
			up->text, up->pid,
			r, r->request.type, r->reply.type, r->request.tag, 
			r->flushtag, r->reply.tag);
		error(Emountrpc);