~kris/9p

9hist

bf18f95188c2946cc09590bdfc520cbf217627a5 — David du Colombier 32 years ago ed6ebeb
Plan 9 from Bell Labs 1994-06-17
7 files changed, 123 insertions(+), 184 deletions(-)

M carrera/dat.h
M carrera/fptrap.c
M carrera/l.s
M carrera/main.c
M carrera/mem.h
M carrera/trap.c
M port/sysproc.c
M carrera/dat.h => carrera/dat.h +1 -1
@@ 15,7 15,7 @@ typedef struct Ureg	Ureg;
/*
 *  parameters for sysproc.c
 */
#define EXEC_MAGIC(magic)	(magic==V_MAGIC||magic==M_MAGIC)
#define AOUT_MAGIC	V_MAGIC

/*
 *  machine dependent definitions used by ../port/dat.h

M carrera/fptrap.c => carrera/fptrap.c +9 -12
@@ 34,10 34,10 @@ fptrap(Ureg *ur)

print("fpt: %d %s %lux\n", up->pid, up->text, up->fpsave.fpstatus);

	iw = ur->pc;
	if(ur->cause & (1<<31))
		iw += 4;
	iw = *(ulong*)iw;
		iw = *(ulong*)(ur->pc+4);
	else
		iw = *(ulong*)ur->pc;

	if(fpunimp(iw) == 0)
		return;


@@ 174,19 174,17 @@ fpunimp(ulong iw)
	return 0;
}

static long*
static ulong*
reg(Ureg *ur, int regno)
{
	/* regs go from R31 down in ureg, R29 is missing */
	switch(regno) {
	case 31:
	if(regno == 31)
		return &ur->r31;
	case 30:
	if(regno == 30)
		return &ur->r30;
	case 29:
	if(regno == 29)
		return &ur->sp;
	}
	return (&ur->r28) + (28-regno)*(&ur->r27-&ur->r28);
	return (&ur->r28) + (28-regno);
}

static ulong


@@ 194,8 192,7 @@ branch(Ureg *ur, ulong fcr31)
{
	ulong iw, npc, rs, rt, rd, offset;

	iw = ur->pc;
	iw = *(ulong*)iw;
	iw = *(ulong*)ur->pc;
	rs = (iw>>21) & 0x1F;
	if(rs)
		rs = *reg(ur, rs);

M carrera/l.s => carrera/l.s +93 -86
@@ 19,18 19,23 @@
#define	LL(base, rt)		WORD	$((060<<26)|((base)<<21)|((rt)<<16))
#define	SC(base, rt)		WORD	$((070<<26)|((base)<<21)|((rt)<<16))

#define DBG(S)	CONST(0xa0001000, R20);CONST(S, R21);MOVW	R21,(R20)

/*
 * Boot first processor
 */
TEXT	start(SB), $-4

DBG(0x55aa0000)
	MOVW	$setR30(SB), R30
	MOVW	$(CU1|INTR7|INTR6|INTR5|INTR4|INTR3|INTR2|INTR1|INTR0), R1
	MOVW	R1, M(STATUS)
	WAIT
DBG(0x55aa0001)

	MOVW	$TLBROFF, R1
	MOVW	R1, M(WIRED)
DBG(0x55aa0002)

	MOVW	$((0x1C<<7)|(1<<24)), R1
	MOVW	R1, FCR31	/* permit only inexact and underflow */


@@ 52,14 57,19 @@ TEXT	start(SB), $-4
	MOVD	F24, F18
	MOVD	F24, F20
	MOVD	F24, F22
DBG(0x55aa0003)

	MOVW	$MACHADDR, R(MACH)
	ADDU	$(BY2PG-4), R(MACH), SP
	MOVW	$0, R(USER)
DBG(0x55aa0010)
MOVW R(MACH),4(R20)
	MOVW	R0, 0(R(MACH))
DBG(0x55aa0011)

	MOVW	$edata(SB), R1
	MOVW	$end(SB), R2
DBG(0x55aa0004)

clrbss:
	MOVB	$0, (R1)


@@ 83,7 93,7 @@ TEXT	touser(SB), $-4
	MOVW	M(STATUS), R4
	WAIT
	AND	$(~KMODEMASK), R4
	OR	$(KUSER|EXL|IE|UX), R4
	OR	$(KUSER|EXL|IE), R4
	MOVW	R4, M(STATUS)
	WAIT
	MOVW	R1, SP


@@ 374,14 384,14 @@ wasuser:
	MOVW	8(R27), R26		/* R26 = m->proc */
	MOVW	8(R26), R27		/* R27 = m->proc->kstack */
	MOVW	SP, R26			/* save user sp */
	ADDU	$(KSTACK-UREGSIZE), R27, SP
	ADDU	$(KSTACK-UREGSIZE-2*BY2WD), R27, SP

	MOVW	R26, Ureg_sp(SP)	/* user SP */
	MOVW	R31, Ureg_r31(SP)
	MOVW	R30, Ureg_r30(SP)
	MOVW	R26, 0x10(SP)			/* user SP */
	MOVW	R31, 0x28(SP)
	MOVW	R30, 0x2C(SP)
	MOVW	M(CAUSE), R26
	MOVW	R(MACH), Ureg_r25(SP)
	MOVW	R(USER), Ureg_r24(SP)
	MOVW	R(MACH), 0x3C(SP)
	MOVW	R(USER), 0x40(SP)
	AND	$(EXCMASK<<2), R26
	SUBU	$(CSYS<<2), R26



@@ 397,13 407,13 @@ wasuser:
	JAL	syscall(SB)

sysrestore:
	MOVW	Ureg_r31(SP), R31
	MOVW	Ureg_status(SP), R26
	MOVW	Ureg_r30(SP), R30
	MOVW	0x28(SP), R31
	MOVW	0x08(SP), R26
	MOVW	0x2C(SP), R30
	MOVW	R26, M(STATUS)
	WAIT
	MOVW	Ureg_pc(SP), R26		/* old pc */
	MOVW	Ureg_sp(SP), SP
	MOVW	0x0C(SP), R26		/* old pc */
	MOVW	0x10(SP), SP
	MOVW	R26, M(EPC)
	ERET



@@ 411,28 421,25 @@ notsys:
	JAL	trap(SB)
restore:
	JAL	restregs(SB)
	MOVW	Ureg_r31(SP), R31
	MOVW	Ureg_r30(SP), R30
	MOVW	Ureg_r25(SP), R(MACH)
	MOVW	Ureg_r24(SP), R(USER)
	MOVW	Ureg_sp(SP), SP
	MOVW	0x28(SP), R31
	MOVW	0x2C(SP), R30
	MOVW	0x3C(SP), R(MACH)
	MOVW	0x40(SP), R(USER)
	MOVW	0x10(SP), SP
	MOVW	R26, M(EPC)
	ERET

waskernel:
	MOVW	SP, R26
	SUBU	$UREGSIZE, SP
	OR	$7, SP
	XOR	$7, SP
	MOVW	R26, Ureg_sp(SP)
	MOVW	R31, Ureg_r31(SP)
	MOVW	$1, R26			/* not syscall */
	MOVW	SP, -(UREGSIZE-16)(SP)
	SUBU	$UREGSIZE, SP
	MOVW	R31, 0x28(SP)
	JAL	saveregs(SB)
	MOVW	4(SP), R1		/* first arg for trap */
	JAL	trap(SB)
	JAL	restregs(SB)
	MOVW	Ureg_r31(SP), R31
	MOVW	Ureg_sp(SP), SP
	MOVW	0x28(SP), R31
	ADDU	$UREGSIZE, SP
	MOVW	R26, M(EPC)
	ERET



@@ 441,21 448,21 @@ TEXT	forkret(SB), $0
	JMP	sysrestore

TEXT	saveregs(SB), $-4
	MOVW	R1, Ureg_r1(SP)
	MOVW	R2, Ureg_r2(SP)
	MOVW	R1, 0x9C(SP)
	MOVW	R2, 0x98(SP)
	/* save R5, R6 as 64 bits */
	ADDU	$(UREGSIZE-16), SP, R1
	MOVW	$~7, R2			/* don't let him use R28 */
	AND		R2, R1
	STD		(5, 0,(1))
	STD		(6, 8,(1))
	ADDU	$Uoffset, SP, R1
	MOVW	R1, 4(SP)		/* arg to base of regs */
	ADDU	$8, SP, R1
	MOVW	R1, 0x04(SP)		/* arg to base of regs */
	MOVW	M(STATUS), R1
	MOVW	M(EPC), R2
	WAIT
	MOVW	R1, Ureg_status(SP)
	MOVW	R2, Ureg_pc(SP)
	MOVW	R1, 0x08(SP)
	MOVW	R2, 0x0C(SP)

	MOVW	$(~KMODEMASK),R2	/* don't let him use R28 */
	AND	R2, R1


@@ 466,74 473,74 @@ TEXT	saveregs(SB), $-4
	MOVW	M(CAUSE), R1
	MOVW	M(BADVADDR), R2
	NOOP
	MOVW	R1, Ureg_cause(SP)
	MOVW	R1, 0x14(SP)
	MOVW	M(TLBVIRT), R1
	NOOP
	MOVW	R2, Ureg_badvaddr(SP)
	MOVW	R1, Ureg_tlbvirt(SP)
	MOVW	R2, 0x18(SP)
	MOVW	R1, 0x1C(SP)
	MOVW	HI, R1
	MOVW	LO, R2
	MOVW	R1, Ureg_hi(SP)
	MOVW	R2, Ureg_lo(SP)
	MOVW	R1, 0x20(SP)
	MOVW	R2, 0x24(SP)
					/* LINK,SB,SP missing */
	MOVW	R28, Ureg_r28(SP)
	MOVW	R28, 0x30(SP)
					/* R27, R26 not saved */
					/* R25, R24 missing */
	MOVW	R23, Ureg_r23(SP)
	MOVW	R22, Ureg_r22(SP)
	MOVW	R21, Ureg_r21(SP)
	MOVW	R20, Ureg_r20(SP)
	MOVW	R19, Ureg_r19(SP)
	MOVW	R18, Ureg_r18(SP)
	MOVW	R17, Ureg_r17(SP)
	MOVW	R16, Ureg_r16(SP)
	MOVW	R15, Ureg_r15(SP)
	MOVW	R14, Ureg_r14(SP)
	MOVW	R13, Ureg_r13(SP)
	MOVW	R12, Ureg_r12(SP)
	MOVW	R11, Ureg_r11(SP)
	MOVW	R10, Ureg_r10(SP)
	MOVW	R9, Ureg_r9(SP)
	MOVW	R8, Ureg_r8(SP)
	MOVW	R7, Ureg_r7(SP)
	MOVW	R6, Ureg_r6(SP)
	MOVW	R5, Ureg_r5(SP)
	MOVW	R4, Ureg_r4(SP)
	MOVW	R3, Ureg_r3(SP)
	MOVW	R23, 0x44(SP)
	MOVW	R22, 0x48(SP)
	MOVW	R21, 0x4C(SP)
	MOVW	R20, 0x50(SP)
	MOVW	R19, 0x54(SP)
	MOVW	R18, 0x58(SP)
	MOVW	R17, 0x5C(SP)
	MOVW	R16, 0x60(SP)
	MOVW	R15, 0x64(SP)
	MOVW	R14, 0x68(SP)
	MOVW	R13, 0x6C(SP)
	MOVW	R12, 0x70(SP)
	MOVW	R11, 0x74(SP)
	MOVW	R10, 0x78(SP)
	MOVW	R9, 0x7C(SP)
	MOVW	R8, 0x80(SP)
	MOVW	R7, 0x84(SP)
	MOVW	R6, 0x88(SP)
	MOVW	R5, 0x8C(SP)
	MOVW	R4, 0x90(SP)
	MOVW	R3, 0x94(SP)
return:
	RET

TEXT	restregs(SB), $-4
					/* LINK,SB,SP missing */
	MOVW	Ureg_r28(SP), R28
	MOVW	0x30(SP), R28
					/* R27, R26 not saved */
					/* R25, R24 missing */
	MOVW	Ureg_r23(SP), R23
	MOVW	Ureg_r22(SP), R22
	MOVW	Ureg_r21(SP), R21
	MOVW	Ureg_r20(SP), R20
	MOVW	Ureg_r19(SP), R19
	MOVW	Ureg_r18(SP), R18
	MOVW	Ureg_r17(SP), R17
	MOVW	Ureg_r16(SP), R16
	MOVW	Ureg_r15(SP), R15
	MOVW	Ureg_r14(SP), R14
	MOVW	Ureg_r13(SP), R13
	MOVW	Ureg_r12(SP), R12
	MOVW	Ureg_r11(SP), R11
	MOVW	Ureg_r10(SP), R10
	MOVW	Ureg_r9(SP), R9
	MOVW	Ureg_r8(SP), R8
	MOVW	Ureg_r7(SP), R7
	MOVW	0x44(SP), R23
	MOVW	0x48(SP), R22
	MOVW	0x4C(SP), R21
	MOVW	0x50(SP), R20
	MOVW	0x54(SP), R19
	MOVW	0x58(SP), R18
	MOVW	0x5C(SP), R17
	MOVW	0x60(SP), R16
	MOVW	0x64(SP), R15
	MOVW	0x68(SP), R14
	MOVW	0x6C(SP), R13
	MOVW	0x70(SP), R12
	MOVW	0x74(SP), R11
	MOVW	0x78(SP), R10
	MOVW	0x7C(SP), R9
	MOVW	0x80(SP), R8
	MOVW	0x84(SP), R7
	/*
	 * restored below
	 * MOVW	Ureg_r6(SP), R6
	 * MOVW	Ureg_r5(SP), R5
	 * MOVW	0x88(SP), R6
	 * MOVW	0x8C(SP), R5
	 */
	MOVW	Ureg_r4(SP), R4
	MOVW	Ureg_r3(SP), R3
	MOVW	Ureg_lo(SP), R2
	MOVW	Ureg_hi(SP), R1
	MOVW	0x90(SP), R4
	MOVW	0x94(SP), R3
	MOVW	0x24(SP), R2
	MOVW	0x20(SP), R1
	MOVW	R2, LO
	MOVW	R1, HI
	/* restore 64-bit R5, R6 */


@@ 542,12 549,12 @@ TEXT	restregs(SB), $-4
	AND		R2, R1
	LD		(0,(1), 5)
	LD		(8,(1), 6)
	MOVW	Ureg_status(SP), R1
	MOVW	Ureg_r2(SP), R2
	MOVW	0x08(SP), R1
	MOVW	0x98(SP), R2
	MOVW	R1, M(STATUS)
	WAIT
	MOVW	Ureg_r1(SP), R1
	MOVW	Ureg_pc(SP), R26
	MOVW	0x9C(SP), R1
	MOVW	0x0C(SP), R26		/* old pc */
	RET

TEXT	rfnote(SB), $0

M carrera/main.c => carrera/main.c +1 -2
@@ 310,8 310,7 @@ iomapinit(void)
void
vecinit(void)
{
	memmove((ulong*)UTLBMISS, (ulong*)vector0, 0x80);
	memmove((ulong*)XEXCEPTION, (ulong*)vector0, 0x80);
	memmove((ulong*)UTLBMISS, (ulong*)vector0, 0x100);
	memmove((ulong*)CACHETRAP, (ulong*)vector100, 0x80);
	memmove((ulong*)EXCEPTION, (ulong*)vector180, 0x80);


M carrera/mem.h => carrera/mem.h +2 -46
@@ 66,7 66,6 @@
#define ERL		0x00000004
#define KSUPER		0x00000008
#define KUSER		0x00000010
#define UX		0x00000020
#define INTMASK		0x0000ff00
#define INTR0		0x00000100
#define INTR1		0x00000200


@@ 99,54 98,11 @@
 * Fundamental addresses
 */
#define	MACHADDR	(KTZERO-MAXMACH*BY2PG)	/* warning: rdbg is near here */
/* Sizeof(Ureg)+R5,R6+16 bytes slop+retpc & ur */
#define	UREGSIZE	0xC0		
#define	MACHP(n)	((Mach *)(MACHADDR+(n)*BY2PG))

/*
 * offsets in ureg.h for l.s
 */
#define	Ureg_status	(Uoffset+0)
#define	Ureg_pc		(Uoffset+4)
#define	Ureg_sp		(Uoffset+8)
#define	Ureg_cause	(Uoffset+12)
#define	Ureg_badvaddr	(Uoffset+16)
#define	Ureg_tlbvirt	(Uoffset+20)
#define	Ureg_hi		(Uoffset+28)
#define	Ureg_lo		(Uoffset+36)
#define	Ureg_r31	(Uoffset+44)
#define	Ureg_r30	(Uoffset+52)
#define	Ureg_r28	(Uoffset+60)
#define	Ureg_r27	(Uoffset+68)
#define	Ureg_r26	(Uoffset+76)
#define	Ureg_r25	(Uoffset+84)
#define	Ureg_r24	(Uoffset+92)
#define	Ureg_r23	(Uoffset+100)
#define	Ureg_r22	(Uoffset+108)
#define	Ureg_r21	(Uoffset+116)
#define	Ureg_r20	(Uoffset+124)
#define	Ureg_r19	(Uoffset+132)
#define	Ureg_r18	(Uoffset+140)
#define	Ureg_r17	(Uoffset+148)
#define	Ureg_r16	(Uoffset+156)
#define	Ureg_r15	(Uoffset+164)
#define	Ureg_r14	(Uoffset+172)
#define	Ureg_r13	(Uoffset+180)
#define	Ureg_r12	(Uoffset+188)
#define	Ureg_r11	(Uoffset+196)
#define	Ureg_r10	(Uoffset+204)
#define	Ureg_r9		(Uoffset+212)
#define	Ureg_r8		(Uoffset+220)
#define	Ureg_r7		(Uoffset+228)
#define	Ureg_r6		(Uoffset+236)
#define	Ureg_r5		(Uoffset+244)
#define	Ureg_r4		(Uoffset+252)
#define	Ureg_r3		(Uoffset+260)
#define	Ureg_r2		(Uoffset+268)
#define	Ureg_r1		(Uoffset+276)
/* Sizeof(Ureg) + (R5,R6) + 16 bytes slop + retpc + ur */
#define	UREGSIZE	((Ureg_r1+4-Uoffset) + 16 + 16 + 4 + 4)
#define	Uoffset		8

/*
 * MMU
 */
#define	PGSZ4K		(0x00<<13)

M carrera/trap.c => carrera/trap.c +16 -36
@@ 253,7 253,7 @@ trap(Ureg *ur)
			postnote(up, 1, buf, NDebug);
			break;
		}
		print("kernel %s pc=%llux\n", excname[ecode], ur->pc);
		print("kernel %s pc=%lux\n", excname[ecode], ur->pc);
		dumpregs(ur);
		dumpstack();
		if(m->machno == 0)


@@ 283,14 283,6 @@ trap(Ureg *ur)
	}
}

struct
{
	ulong cause;
	ulong devint3;
	ulong devint4;
	ulong state;
}sisr;

void
intr(Ureg *ur)
{


@@ 300,11 292,9 @@ intr(Ureg *ur)

	m->intr++;
	cause &= INTR7|INTR6|INTR5|INTR4|INTR3|INTR2|INTR1|INTR0;
sisr.cause = cause;

	if(cause & INTR3) {
		devint = IO(uchar, Intcause);
sisr.devint3 = devint;
sisr.state = 0;
		switch(devint) {
		default:
			panic("unknown devint=#%lux", devint);


@@ 328,11 318,9 @@ sisr.state = 0;
			break;
		}
		cause &= ~INTR3;
sisr.state = 1;
	}

	if(cause & INTR2) {
sisr.state = 2;
		isr = IO(ulong, R4030Isr);
		if(isr) {
			iprint("R4030 Interrupt\n");


@@ 342,14 330,12 @@ sisr.state = 2;
			iprint(" MFA #%lux\n", IO(ulong, R4030Mfa));
		}
		cause &= ~INTR2;
sisr.state = 3;
	}

	if(cause & INTR4) {
		devint = IO(uchar, I386ack);
		vec = devint&~0x7;
sisr.devint4 = devint;
sisr.state = 4;

		/* reenable the 8259 interrupt */
		if(vec == Int0vec || vec == Int1vec){
			EISAOUTB(Int0ctl, EOI);


@@ 362,18 348,13 @@ sisr.state = 4;
			iprint("i386ACK #%lux\n", devint);
			break;
		case 7:
sisr.state = 5;
			audiosbintr();
sisr.state = 6;
			break;
		case 13:
sisr.state = 7;
			audiodmaintr();
sisr.state = 8;
			break;
		}
		cause &= ~INTR4;
sisr.state = 9;
	}

	if(cause & INTR7) {


@@ 392,7 373,7 @@ fpexcname(Ureg *ur, ulong fcr31, char *buf)
{
	int i;
	char *s;
	uvlong fppc;
	ulong fppc;

	fppc = ur->pc;
	if(ur->cause & (1<<31))	/* branch delay */


@@ 411,7 392,7 @@ fpexcname(Ureg *ur, ulong fcr31, char *buf)
	if(s == 0)
		return "no floating point exception";

	sprint(buf, "%s fppc=0x%llux", s, fppc);
	sprint(buf, "%s fppc=0x%lux", s, fppc);
	return buf;
}



@@ 421,7 402,7 @@ void
kernfault(Ureg *ur, int code)
{
	print("kfault %s badvaddr=0x%lux\n", excname[code], ur->badvaddr);
	print("UP=0x%lux SR=0x%lux PC=0x%llux R31=%llux SP=0x%llux\n",
	print("UP=0x%lux SR=0x%lux PC=0x%lux R31=%lux SP=0x%lux\n",
				up, ur->status, ur->pc, ur->r31, ur->sp);

	dumpregs(ur);


@@ 484,10 465,10 @@ notify(Ureg *ur)
	n = &up->note[0];
	if(strncmp(n->msg, "sys:", 4) == 0) {
		l = strlen(n->msg);
		if(l > ERRLEN-23)	/* " pc=0x12345678\0" */
			l = ERRLEN-23;
		if(l > ERRLEN-15)	/* " pc=0x12345678\0" */
			l = ERRLEN-15;

		sprint(n->msg+l, " pc=0x%llux", ur->pc);
		sprint(n->msg+l, " pc=0x%lux", ur->pc);
	}

	if(n->flag != NUser && (up->notified || up->notify==0)) {


@@ 509,11 490,10 @@ notify(Ureg *ur)
		pexit(n->msg, n->flag!=NDebug);
	}
	up->svstatus = ur->status;
	sp = ur->usp & ~(BY2V-1);
	sp -= sizeof(Ureg);
	sp = ur->usp - sizeof(Ureg);

	if(!okaddr((ulong)up->notify, BY2WD, 0) ||
	   !okaddr(sp-ERRLEN-3*BY2WD, sizeof(Ureg)+ERRLEN-3*BY2WD, 1)) {
	if(sp&0x3 || !okaddr((ulong)up->notify, BY2WD, 0)
	|| !okaddr(sp-ERRLEN-3*BY2WD, sizeof(Ureg)+ERRLEN-3*BY2WD, 1)) {
		pprint("suicide: bad address or sp in notify\n");
		qunlock(&up->debug);
		pexit("Suicide", 0);


@@ 527,8 507,8 @@ notify(Ureg *ur)
	*(ulong*)(sp+2*BY2WD) = sp+3*BY2WD;	/* arg 2 is string */
	up->svr1 = ur->r1;			/* save away r1 */
	ur->r1 = (ulong)up->ureg;		/* arg 1 is ureg* */
	((ulong*)sp)[1] = (ulong)up->ureg;	/* arg 1 0(FP) is ureg* */
	((ulong*)sp)[0] = 0;			/* arg 0 is pc */
	*(ulong*)(sp+1*BY2WD) = (ulong)up->ureg;	/* arg 1 0(FP) is ureg* */
	*(ulong*)(sp+0*BY2WD) = 0;		/* arg 0 is pc */
	ur->usp = sp;
	ur->pc = (ulong)up->notify;
	up->notified = 1;


@@ 627,13 607,13 @@ syscall(Ureg *aur)
		goto error;

	if(up->scallnr >= nsyscall){
		pprint("bad sys call %d pc %llux\n", up->scallnr, ur->pc);
		pprint("bad sys call %d pc %lux\n", up->scallnr, ur->pc);
		postnote(up, 1, "sys: bad sys call", NDebug);
		error(Ebadarg);
	}

	if(sp & (BY2WD-1)){
		pprint("odd sp in sys call pc %llux sp %llux\n", ur->pc, ur->sp);
		pprint("odd sp in sys call pc %lux sp %lux\n", ur->pc, ur->sp);
		postnote(up, 1, "sys: odd stack", NDebug);
		error(Ebadarg);
	}

M port/sysproc.c => port/sysproc.c +1 -1
@@ 215,7 215,7 @@ sysexec(ulong *arg)
	magic = l2be(exec.magic);
	text = l2be(exec.text);
	entry = l2be(exec.entry);
	if(n==sizeof(Exec) && EXEC_MAGIC(magic)){
	if(n==sizeof(Exec) && magic == AOUT_MAGIC){
		if((text&KZERO)
		|| entry < UTZERO+sizeof(Exec)
		|| entry >= UTZERO+sizeof(Exec)+text)