From b24f48e95ba5d5417b32c6dcda15c313ceaff5bf Mon Sep 17 00:00:00 2001
From: David du Colombier <0intro@gmail.com>
Date: Tue, 15 Apr 2003 00:00:00 +0000
Subject: [PATCH] Plan 9 from Bell Labs 2003-04-15

---
 pc/sd53c8xx.c |  4 ++--
 pc/sdata.c    | 17 +++++++++++++++++
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/pc/sd53c8xx.c b/pc/sd53c8xx.c
index c90d5cdb396d90e85069ac6702359b998dfbc3d4..f956e0132b4ff49bf09b0e64bba3160ddb799311 100644
--- a/pc/sd53c8xx.c
+++ b/pc/sd53c8xx.c
@@ -52,8 +52,8 @@ extern SDifc sd53c8xxifc;
 
 #else
 
-#define KPRINT	if(1) print
-#define IPRINT	if(1) print
+#define KPRINT	if(0) print
+#define IPRINT	if(0) print
 #define DEBUG(n)	(0)
 #define IFLUSH()
 
diff --git a/pc/sdata.c b/pc/sdata.c
index b412e27b248a2b652692a840dbf7ea65bf316cf8..deab9cb4b3a7b3bd7deae303a44e1ddf52c3c57e 100644
--- a/pc/sdata.c
+++ b/pc/sdata.c
@@ -1721,6 +1721,23 @@ atapnp(void)
 			 * Bugfix code here...
 			 */
 			break;
+		case (0x7441<<16)|0x1022:	/* AMD 768 */
+			/*
+			 * Set:
+			 *	0x41	prefetch, postwrite;
+			 *	0x43	FIFO configuration 1/2 and 1/2;
+			 *	0x44	status register read retry;
+			 *	0x46	DMA read and end of sector flush.
+			 */
+			r = pcicfgr8(p, 0x41);
+			pcicfgw8(p, 0x41, r|0xF0);
+			r = pcicfgr8(p, 0x43);
+			pcicfgw8(p, 0x43, (r & 0x90)|0x2A);
+			r = pcicfgr8(p, 0x44);
+			pcicfgw8(p, 0x44, r|0x08);
+			r = pcicfgr8(p, 0x46);
+			pcicfgw8(p, 0x46, (r & 0x0C)|0xF0);
+			break;
 		case (0x0646<<16)|0x1095:	/* CMD 646 */
 		case (0x0571<<16)|0x1106:	/* VIA 82C686 */
 		case (0x0211<<16)|0x1166:	/* ServerWorks IB6566 */