From ad718a20afbbd9fadfeb0180d0ee3cc586d3b7ea Mon Sep 17 00:00:00 2001 From: David du Colombier <0intro@gmail.com> Date: Sat, 18 Aug 2001 00:00:00 +0000 Subject: [PATCH] Plan 9 from Bell Labs 2001-08-18 --- bitsy/fns.h | 1 + bitsy/io.h | 31 +++++++------ bitsy/l.s | 120 ++++++++++++++++++++++++++------------------------ bitsy/power.c | 22 +++++---- 4 files changed, 95 insertions(+), 79 deletions(-) diff --git a/bitsy/fns.h b/bitsy/fns.h index f6b6edcb2c99eb255751e9052520f1fccdd7dd72..d754660afb88c433d56a8919352b71c8f94112b4 100644 --- a/bitsy/fns.h +++ b/bitsy/fns.h @@ -77,6 +77,7 @@ PCMmap* pcmmap(int, ulong, int, int); void pcmunmap(int, PCMmap*); void penbutton(int, int); void pentrackxy(int x, int y); +void power_down(void); void powerinit(void); void powerkproc(void*); #define procrestore(p) diff --git a/bitsy/io.h b/bitsy/io.h index bcac6f2767cdee0ada1e40a8070de9e2d79d4ce9..2c99d711d10178cca9912b81c264c0b7b8602c64 100644 --- a/bitsy/io.h +++ b/bitsy/io.h @@ -223,24 +223,29 @@ enum MECR_attr1= MECR_attr0+16, MECR_mem1= MECR_mem0+16, MECR_fast1= MECR_fast0+16, + + REFR_kapd= 29, + REFR_eapd= 28, + REFR_k1db2= 22, + REFR_slfrsh= 31, }; typedef struct MemConfRegs MemConfRegs; struct MemConfRegs { - ulong mdcnfg; /* dram */ - ulong mdcas00; /* dram banks 0/1 */ - ulong mdcas01; - ulong mdcas02; - ulong msc0; /* static */ - ulong msc1; - ulong mecr; /* pcmcia */ - ulong mdrefr; /* dram refresh */ - ulong mdcas20; /* dram banks 2/3 */ - ulong mdcas21; - ulong mdcas22; - ulong msc2; /* static */ - ulong smcnfg; /* SMROM config */ + ulong mdcnfg; /* 0x00 dram */ + ulong mdcas00; /* 0x04 dram banks 0/1 */ + ulong mdcas01; /* 0x08 */ + ulong mdcas02; /* 0x0c */ + ulong msc0; /* 0x10 static */ + ulong msc1; /* 0x14 */ + ulong mecr; /* 0x18 pcmcia */ + ulong mdrefr; /* 0x1c dram refresh */ + ulong mdcas20; /* 0x20 dram banks 2/3 */ + ulong mdcas21; /* 0x24 */ + ulong mdcas22; /* 0x28 */ + ulong msc2; /* 0x2c static */ + ulong smcnfg; /* 0x30 SMROM config */ }; extern MemConfRegs *memconfregs; diff --git a/bitsy/l.s b/bitsy/l.s index da51ca879ee5f4c4557f6637794ec8fad1bf80ae..0dad65f8b89b7ff8fb7d96b716f8efe4a6fecdb6 100644 --- a/bitsy/l.s +++ b/bitsy/l.s @@ -670,31 +670,35 @@ TEXT sa1100_power_resume(SB), $-4 loop: B loop -TEXT sa1100_power_down(SB), $-4 +TEXT power_down(SB), $-4 /* disable clock switching */ MCR CpPWR, 0, R0, C(CpTest), C(0x2), 2 - /* save address of sleep_param in r4 */ - mov r0, r4 - - @ Adjust memory timing before lowering CPU clock - /* Clock speed ajdustment without changing memory timing makes */ - /* CPU hang in some cases */ - ldr r0, =MDREFR - ldr r1, [r0] - orr r1, r1, #MDREFR_K1DB2 - str r1, [r0] + /* Adjust memory timing before lowering CPU clock + * Clock speed ajdustment without changing memory + * timing makes CPU hang in some cases + */ + MOVW $(MEMCONFREGS+0x1c),R0 + MOVW (R0),R1 /* mdrefr */ + ORR $(1<<22), R1 /* set K1DB2 */ + MOVW R1,(R0) /* delay 90us and set CPU PLL to lowest speed */ /* fixes resume problem on high speed SA1110 */ - mov r0, #90 - bl SYMBOL_NAME(udelay) - ldr r0, =PPCR - mov r1, #0 - str r1, [r0] - mov r0, #90 - bl SYMBOL_NAME(udelay) + MOVW $(90*206),R0 +d1: + SUB $1,R0 + BNE d1 + + MOVW $(POWERREGS+0x14),R0 + MOVW $0,R1 + MOVW R1,(R0) /* clear PPCR */ + + MOVW $(90*206),R0 +d2: + SUB $1,R0 + BNE d2 /* setup up register contents for jump to page containing SA1110 SDRAM controller bug fix suspend code @@ -716,72 +720,72 @@ TEXT sa1100_power_down(SB), $-4 * */ - ldr r0, =MSC0 - ldr r1, =MSC1 - ldr r2, =MSC2 + MOVW $(MEMCONFREGS+0x10),R0 + MOVW $(MEMCONFREGS+0x14),R1 + MOVW $(MEMCONFREGS+0x2c),R2 - ldr r3, [r0] - bic r3, r3, #FMsk(MSC_RT) - bic r3, r3, #FMsk(MSC_RT)<<16 + MOVW (R0),R3 + BIC $0x00030003,R3 /* MSC_RT fields */ - ldr r4, [r1] - bic r4, r4, #FMsk(MSC_RT) - bic r4, r4, #FMsk(MSC_RT)<<16 + MOVW (R1),R4 + BIC $0x00030003,R4 /* MSC_RT fields */ - ldr r5, [r2] - bic r5, r5, #FMsk(MSC_RT) - bic r5, r5, #FMsk(MSC_RT)<<16 + MOVW (R2),R5 + BIC $0x00030003,R5 /* MSC_RT fields */ - ldr r6, =MDREFR + MOVW $(MEMCONFREGS+0x1c),R6 - ldr r7, [r6] - bic r7, r7, #0x0000FF00 - bic r7, r7, #0x000000F0 - orr r8, r7, #MDREFR_SLFRSH + MOVW (R6),R7 + BIC $0x0000FFF0,R7 /* DRI 0 .. 11 */ + ORR $(1<<31),R7,R8 /* prepare to set self refresh */ - ldr r9, =MDCNFG - ldr r10, [r9] - bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1) - bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3) + MOVW $(MEMCONFREGS+0x0),R9 + MOVW (R9),R10 + BIC $(0x00030003),R10 /* clear DE0 ⋯ DE3 */ - bic r11, r8, #MDREFR_SLFRSH - bic r11, r11, #MDREFR_E1PIN + BIC $(1<<31 | 1<<20),R8,R11 /* self-refresh and e1pin */ - ldr r12, =PMCR + MOVW $(POWERREGS+0x0),R12 + MOVW $1,R13 /* sleep force bit */ - mov r13, #PMCR_SF - - b sa1110_sdram_controller_fix + MOVW R0,R0 + MOVW R0,R0 + MOVW R0,R0 + MOVW R0,R0 + MOVW R0,R0 + MOVW R0,R0 + MOVW R0,R0 + /* Fall through */ - .align 5 -sa1110_sdram_controller_fix: +/* .align 5 Needs to be on a cache line boundary? */ + TEXT sdram_controller_fix(SB),$0 /* Step 1 clear RT field of all MSCx registers */ - str r3, [r0] - str r4, [r1] - str r5, [r2] + MOVW R3,(R0) + MOVW R4,(R1) + MOVW R5,(R2) /* Step 2 clear DRI field in MDREFR */ - str r7, [r6] + MOVW R7,(R6) /* Step 3 set SLFRSH bit in MDREFR */ - str r8, [r6] + MOVW R8,(R6) /* Step 4 clear DE bis in MDCNFG */ - str r10, [r9] + MOVW R10,(R9) /* Step 5 clear DRAM refresh control register */ - str r11, [r6] + MOVW R11,(R6) /* Wow, now the hardware suspend request pins can be used, that makes them functional for */ /* about 7 ns out of the entire time that the CPU is running! */ /* Step 6 set force sleep bit in PMCR */ - str r13, [r12] - -20: - b 20b /* loop waiting for sleep */ + MOVW R13,(R12) + +slloop: + B slloop /* loop waiting for sleep */ /* The first MCR instruction of this function needs to be on a cache-line * boundary; to make this happen, it will be copied (in trap.c). diff --git a/bitsy/power.c b/bitsy/power.c index dfb5169968ad910db489bae39d85197e9858ecca..232ee539591548895a09040a8c3b91cf58d05e1e 100644 --- a/bitsy/power.c +++ b/bitsy/power.c @@ -146,8 +146,11 @@ void (*restart)(void) = nil; static void sa1100_power_off(void) { + ulong refr; + /* Set KAPD and EAPD bits */ -// memconfregs->mdrefr |= 0x30000000; + refr = memconfregs->mdrefr; + refr |= 1<direction = 0; - delay(100); - /* enter sleep mode */ /* set lowest clock; delay to avoid resume hangs on fast sa1110 */ -/* Doesn't work [sjm] + memconfregs->mdrefr |= 1<<22; + µdelay(90); powerregs->ppcr = 0; - delay(500); -*/ - - memconfregs->mdrefr |= 0x80000000; + µdelay(90); + + memconfregs->msc0 &= ~0x30003; + memconfregs->msc1 &= ~0x30003; + memconfregs->msc2 &= ~0x30003; + memconfregs->mdrefr = refr; /* Clear dri 0 ⋯ 11 */ + refr |= 1<mdrefr = refr; /* Set selfrefresh */ powerregs->pmcr = PCFR_suspend; for(;;); }