5 files changed, 94 insertions(+), 102 deletions(-)

M mpc/fns.h
M mpc/l.s
M mpc/main.c
M mpc/mem.h
M mpc/mmu.c

@@ 10,7 10,7 @@ void	clockcheck(void);
 void	clockinit(void);
 void	clockintr(Ureg*);
 void	clrfptrap(void);
-#define coherence()		// not need on signle processor machines
+#define coherence()		// not need on single processor machines
 void	cpminit(void);
 int	cpuidentify(void);
 void	cpuidprint(void);


@@ 19,7 19,8 @@ void	delay(int);
 ulong	draminit(ulong*);
 void	dtlbmiss(void);
 void	dumpregs(Ureg*);
-void	eieio(void);
+//void	eieio(void);
+#define	eieio()
 void	evenaddr(ulong);
 void	faultpower(Ureg*);
 void	firmware(int);


@@ 49,6 50,7 @@ void	itlbmiss(void);
 int	isaconfig(char*, int, ISAConf*);
 void	kbdinit(void);
 void	kbdreset(void);
+void	kernelmmu(void);
 void	links(void);
 void	mapfree(RMap*, ulong, int);
 void	mapinit(RMap*, Map*, int);

@@ 143,27 143,42 @@ clrbss:
 	CMP	R3, R4
 	BNE	clrbss
 
+	/* off to main */
 	BL	main(SB)
 	BR	0(PC)
 
+
 TEXT	kernelmmu(SB), $0
-	TLBIA
-	ISYNC
 
+	/* dont use CASID yet - set to zero for now */
 	MOVW	$0, R4
-	MOVW	R4, SPR(M_CASID)	/* set supervisor space */
-	MOVW	$(0<<29), R4		/* allow i-cache when IR=0 */
+	MOVW	R4, SPR(M_CASID)
+	
+	/* set Ks = 0 Kp = 1 for all acess groups */
+	MOVW	$0x55555555, R4
+	MOVW	R4, SPR(MI_AP)
+	MOVW	R4, SPR(MD_AP)
+
+	/*
+	 * set:
+	 *  PowerPC mode
+	 *  Page protection mode - no 1K pages
+	 *  CI when MMU is disbaled - this will change
+	 *  WT when DMMU is disbaled - this will change
+	 *  disable protected TLB for the momment
+	 *  ignore user/supervisor state when looking for TLB
+	 *  set first tlb entry to 28 - first lockable entry
+	 */
+	MOVW	$(MMUCIDEF|(31<<8)), R4
 	MOVW	R4, SPR(MI_CTR)	/* i-mmu control */
 	ISYNC
-	MOVW	$((1<<29)|(1<<28)), R4	/* cache inhibit when DR=0, write-through */
-	SYNC
+	MOVW	$(MMUCIDEF|MMUWTDEF|(31<<8)), R4
 	MOVW	R4, SPR(MD_CTR)	/* d-mmu control */
 	ISYNC
-	TLBIA
 
 	/* map various things 1:1 */
-	MOVW	$tlbtab-KZERO(SB), R4
-	MOVW	$tlbtabe-KZERO(SB), R5
+	MOVW	$tlbtab(SB), R4
+	MOVW	$tlbtabe(SB), R5
 	SUB	R4, R5
 	MOVW	$(3*4), R6
 	DIVW	R6, R5


@@ 181,29 196,13 @@ ltlb:
 	MOVW	R5, SPR(MI_RPN)
 	BDNZ	ltlb
 
-	MOVW	$(1<<25), R4
-	MOVW	R4, SPR(IC_CST)	/* enable i-cache */
-	ISYNC
-
-	MOVW	$(1<<24), R4
-	SYNC
-	MOVW	R4, SPR(DC_CST)	/* force write through mode */
-	MOVW	$(1<<25), R4
-	SYNC
-	MOVW	R4, SPR(DC_CST)	/* enable d-cache */
+	/* enable MMU */
+	MOVW	MSR, R4
+	OR	$(MSR_IR|MSR_DR), R4
+	MOVW	R4, MSR
 	ISYNC
 
-	/* enable MMU and set kernel PC to virtual space */
-	MOVW	$((0<<29)|(1<<28)), R4	/* cache when DR=0, write-through */
-	SYNC
-	MOVW	R4, SPR(MD_CTR)	/* d-mmu control */
-	MOVW	LR, R3
-	OR	$KZERO, R3
-	MOVW	R3, SPR(SRR0)
-	MOVW	MSR, R4
-	OR	$(MSR_ME|MSR_IR|MSR_DR), R4	/* had ME|FPE|FE0|FE1 */
-	MOVW	R4, SPR(SRR1)
-	RFI	/* resume in kernel mode in caller */
+	RETURN
 
 TEXT	splhi(SB), $0
 	MOVW	MSR, R3


@@ 384,11 383,11 @@ TEXT	getcallerpc(SB), $-4
 	MOVW	0(R1), R3
 	RETURN
 
-TEXT getdar(SB), $0
+TEXT	getdar(SB), $0
 	MOVW	SPR(DAR), R3
 	RETURN
 
-TEXT getdsisr(SB), $0
+TEXT	getdsisr(SB), $0
 	MOVW	SPR(DSISR), R3
 	RETURN
 


@@ 410,6 409,13 @@ TEXT	eieio(SB), $0
 	EIEIO
 	RETURN
 
+TEXT	flushmmu(SB), $0
+	TLBIA
+	RETURN
+
+TEXT	putmmu(SB), $0
+	RETURN
+
 TEXT	gotopc(SB), $0
 	MOVW	R3, CTR
 	MOVW	LR, R31	/* for trace back */


@@ 609,22 615,19 @@ GLOBL	spltbl+0(SB), $4
 GLOBL	intrtbl+0(SB), $4
 GLOBL	isavetbl+0(SB), $4
 
+	RETURN
+
 /*
  * TLB prototype entries, loaded once-for-all at startup,
  * remaining unchanged thereafter.
- * Limit the table to at most 8 entries to ensure
- * it works on the 823 (other 8xx processors allow up to 32 TLB entries).
+ * Limit the table to at most 4 entries
  */
-#define	TLBE(epn,rpn,twc)	WORD	$(epn);  WORD	$(twc); WORD	$(rpn)
+#define	TLBE(epn,twc,rpn)	WORD	$(epn);	WORD	$(twc);	WORD	$(rpn)
 
 TEXT	tlbtab(SB), $-4
-
 	/* epn, rpn, twc */
-/*	TLBE(KZERO|DRAMMEM|TLBVALID, DRAMMEM|PTEWRITE|PTELPS|PTESH|PTEVALID, PTE8MB|PTEWT|PTEVALID)	/* DRAM, 8M */
-/*	TLBE(KZERO|BCSRMEM|TLBVALID, BCSRMEM|PTEWRITE|PTESH|PTECI|PTEVALID, PTE4K|PTEWT|PTEVALID)	/* Board CSR, 4K */
-/*	TLBE(KZERO|INTMEM|TLBVALID, INTMEM|PTEWRITE|PTELPS|PTESH|PTECI|PTEVALID, PTE4K|PTEWT|PTEVALID)	/* IMMR, 16K */
-/*	TLBE(KZERO|FLASHMEM|TLBVALID, FLASHMEM|PTEWRITE|PTELPS|PTESH|PTECI|PTEVALID, PTE8MB|PTEWT|PTEVALID)	/* Flash, 8M */
-/*	TLBE(KZERO|SDRAMMEM|TLBVALID, SDRAMMEM|PTEWRITE|PTELPS|PTESH|PTEVALID, PTE8MB|PTEWT|PTEVALID)	/* SDRAM, 8M */
-/*	TLBE(KZERO|PCMCIAMEM|TLBVALID, PCMCIAMEM|PTEWRITE|PTELPS|PTESH|PTECI|PTEVALID, PTE8MB|PTEWT|PTEVALID)	/* PCMCIA, 8M */
+	TLBE(DRAMMEM|MMUEV, MMUPS8M|MMUWT|MMUV, DRAMMEM|MMUPP|MMUSPS|MMUSH|MMUCI|MMUV)	/* DRAM, 8M */
+	TLBE((DRAMMEM+8*(1<<20))|MMUEV, MMUPS8M|MMUWT|MMUV, (DRAMMEM+8*(1<<20))|MMUPP|MMUSPS|MMUSH|MMUCI|MMUV)	/* DRAM, second 8M */
+	TLBE(INTMEM|MMUEV, MMUPS8M|MMUWT|MMUV, INTMEM|MMUPP|MMUSPS|MMUSH|MMUCI|MMUV)	/* IO space 8M */
 TEXT	tlbtabe(SB), $-4
 	RETURN

@@ 40,7 40,7 @@ main(void)
 	printinit();
 	cpminit();
 	uartinstall();
-delay(500);
+	mmuinit();
 	spllo();
 	for(i=0; ; i++) {
 		print("hello again %d\n", i);


@@ 136,8 136,8 @@ iprint(char *fmt, ...)
 	n = doprint(buf, buf+sizeof(buf), fmt, arg) - buf;
 	va_end(arg);
 
-//	putstrn(buf, n);
-//	uartwait();
+	putstrn(buf, n);
+	uartwait();
 
 	return n;
 }

@@ 102,8 102,8 @@
  * MMU
  */
 
+#ifdef notdef
 /* L1 table entry and Mx_TWC flags */
-#define PTEVALID	(1<<0)
 #define PTEWT		(1<<1)	/* write through */
 #define PTE4K		(0<<2)
 #define PTE512K		(1<<2)


@@ 114,21 114,48 @@
 #define PTECI		(1<<1)	/*  cache inhibit */
 #define PTESH		(1<<2)	/* page is shared; ASID ignored */
 #define PTELPS		(1<<3)	/* large page size */
-#define PTEWRITE	0x9F0
 
-/*
- *  physical MMU - bogus at the momement
- */
-#define	PTEUNCACHED	(1<<4)
-#define	PTERONLY	(0<<1)
 #define	PTEKERNEL	(0<<2)
 #define	PTEUSER		(1<<2)
 #define PTESIZE		(1<<7)
+#endif
+/*
+ *  portable MMU bits for fault.c - though still machine specific
+ */
+#define PTEVALID	(1<<0) 
+#define PTEWRITE	(2<<10)
+#define	PTERONLY	(3<<10)
+#define	PTEUNCACHED	(1<<4)
 
-/* TLB and MxEPN flag */
-#define	TLBVALID	(1<<9)
+/*
+ * physical MMU bits
+ */
 
-#define	TLBSETS	32	/* number of tlb sets */
+/* Mx_CTR */
+#define MMUGPM		(1<<31)	/* group protection mode */
+#define	MMUPPM		(1<<30)	/* page protect mode */
+#define MMUCIDEF	(1<<29)	/* default CI value when MMU is disabled */
+#define MMUWTDEF	(1<<28)	/* default WT value when MMU is disabled */
+#define MMURSV4		(1<<27) /* reserve 4 TLB entries */
+#define MMUTWAM		(1<<26) /* table walk assist mode */
+#define	MMUPPCS		(1<<25) /* privilege/user compare mode */
+
+/* Mx_EPN */
+#define MMUEV		(1<<9)	/* TLB entry valid */
+
+/* Mx_TWC */
+#define	MMUG		(1<<4)	/* guard */
+#define MMUPS4K		(0<<2)	/* 4K or 16K pages */
+#define MMUPS512K	(1<<2)	/* 512K pages */
+#define MMUPS8M		(3<<2)	/* 8M pages */
+#define MMUWT		(1<<1)	/* write through */
+#define MMUV		(1<<0)	/* valid */
+
+/* Mx_RPN */
+#define MMUPP		(0x1f<<4) /* page protection defaults */
+#define MMUSPS		(1<<3)	/* small page size */
+#define MMUSH		(1<<2)	/* shared page */
+#define MMUCI		(1<<1)	/* cache inhibit */
 
 /*
  *  Address spaces


@@ 153,7 180,7 @@
 #define	FLASH0MEM	0x80200000
 #define	FLASH1MEM	0x80400000
 #define	SDRAMMEM	0x03000000
-#define DRAMMEM		0xff000000		// to 0xffffffff: 16 Meg
+#define DRAMMEM		0xff000000		/* to 0xffffffff: 16 Meg */
 
 #define	SIRAM	(INTMEM+0xC00)
 #define	LCDCOLR	(INTMEM+0xE00)

@@ 6,32 6,17 @@
 #include	"io.h"
 
 
-static void
-taskswitch(ulong pdb, ulong stack)
-{
-	USED(pdb, stack);
-}
-
 void
 mmuinit(void)
 {
+iprint("mmuinit\n");
+	kernelmmu();
 }
 
 void
-flushmmu(void)
-{
-}
-
-static void
-mmuptefree(Proc* proc)
-{
-	USED(proc);
-}
-
-void
-mmuswitch(Proc* proc)
+mmuswitch(Proc*)
 {
-	USED(proc);
+	flushmmu();
 }
 
 void


@@ 40,29 25,4 @@ mmurelease(Proc* proc)
 	USED(proc);
 }
 
-static Page*
-mmupdballoc(void)
-{
-}
-
-void
-putmmu(ulong va, ulong pa, Page*)
-{
-	USED(va, pa);
-}
 
-static Lock mmukmaplock;
-
-int
-mmukmapsync(ulong va)
-{
-	USED(va);
-	return 0;
-}
-
-ulong
-mmukmap(ulong pa, ulong va, int size)
-{
-	USED(pa, va, size);
-	return 0;
-}