From 9bc6f5b5e2fd90634dfadc8b27569d406b6d6597 Mon Sep 17 00:00:00 2001 From: David du Colombier <0intro@gmail.com> Date: Sat, 1 Jul 2000 00:00:00 +0000 Subject: [PATCH] Plan 9 from Bell Labs 2000-07-01 --- pc/fns.h | 12 ++++++------ pc/i8253.c | 16 +++++++++++++--- pc/sd53c8xx.c | 12 ++++++++++-- pc/vgas3.c | 2 ++ 4 files changed, 31 insertions(+), 11 deletions(-) diff --git a/pc/fns.h b/pc/fns.h index 3036badddcafd5f1dac9e389a9f811a83aa005b5..465aae9db0c9b59a7175d57617955f981a921feb 100644 --- a/pc/fns.h +++ b/pc/fns.h @@ -1,24 +1,23 @@ #include "../port/portfns.h" -vlong checkcycintr(Ureg*, void*); -void cycintradd(Cycintr*); -void cycintrdel(Cycintr*); -void clockintrsched(void); -vlong cycintrnext(void); - void aamloop(int); void addconf(char*, char*); //void addscsilink(char*, Scsiio (*)(int, ISAConf*)); void archinit(void); void bootargs(ulong); +vlong checkcycintr(Ureg*, void*); int cistrcmp(char*, char*); int cistrncmp(char*, char*, int); #define clearmmucache() /* x86 doesn't have one */ void clockintr(Ureg*, void*); +void clockintrsched(void); void (*coherence)(void); void cpuid(char*, int*, int*); int cpuidentify(void); void cpuidprint(void); +void cycintradd(Cycintr*); +void cycintrdel(Cycintr*); +vlong cycintrnext(void); void delay(int); int dmacount(int); int dmadone(int); @@ -37,6 +36,7 @@ ulong getcr2(void); ulong getcr3(void); ulong getcr4(void); char* getconf(char*); +int havecycintr(void); int i8042auxcmd(int); void i8042auxenable(void (*)(int, int)); void i8042reset(void); diff --git a/pc/i8253.c b/pc/i8253.c index 3e7f69db7838851fee34dc2abec23266a3a68593..9b6d479782fc1dd21d8d00f67d8743e8dfa342a3 100644 --- a/pc/i8253.c +++ b/pc/i8253.c @@ -53,6 +53,7 @@ enum static struct { Lock; + int enabled; int mode; vlong when; /* next fastticks a clock interrupt should occur */ vlong cycwhen; /* next fastticks a cycintr happens; 0 == infinity */ @@ -198,15 +199,23 @@ clockintrsched0(vlong next) } } +int +havecycintr(void) +{ + return i8253.enabled; +} + void clockintrsched(void) { vlong next; ilock(&i8253); - next = cycintrnext(); - if(next != i8253.cycwhen) - clockintrsched0(next); + if(i8253.enabled){ + next = cycintrnext(); + if(next != i8253.cycwhen) + clockintrsched0(next); + } iunlock(&i8253); } @@ -233,6 +242,7 @@ i8253enable(void) i8253.when = fastticks(nil); i8253.fastperiod = (m->cpuhz + HZ/2) / HZ; i8253.fast2freq = (vlong)m->cpuhz * FreqMul / Freq; + i8253.enabled = 1; intrenable(IrqCLOCK, clockintr0, 0, BUSUNKNOWN, "clock"); } diff --git a/pc/sd53c8xx.c b/pc/sd53c8xx.c index c9a1dc2058761fa2d9a220884f01e95349ee7545..7a7a45c97eeeb94dfeca0f9536363d49202830b1 100644 --- a/pc/sd53c8xx.c +++ b/pc/sd53c8xx.c @@ -1938,17 +1938,23 @@ na_fixup(Controller *c, ulong pa_reg, static SDev* sympnp(void) { - int ba; + char *cp; Pcidev *p; Variant *v; + int ba, nctlr; void *scriptma; Controller *ctlr; SDev *sdev, *head, *tail; ulong regpa, *script, scriptpa; + if(cp = getconf("*maxsd53c8xx")) + nctlr = strtoul(cp, 0, 0); + else + nctlr = 32; + p = nil; head = tail = nil; - while(p = pcimatch(p, NCR_VID, 0)){ + while((p = pcimatch(p, NCR_VID, 0)) != nil && nctlr > 0){ for(v = variant; v < &variant[nelem(variant)]; v++){ if(p->did == v->did && p->rid <= v->maxrid) break; @@ -2045,6 +2051,8 @@ buggery: else head = sdev; tail = sdev; + + nctlr--; } return head; diff --git a/pc/vgas3.c b/pc/vgas3.c index 089bd275b3b88af5161ece95253a990f9d97060e..4fc38f5dd0140bedcea341fe50318ec1bd0a17e1 100644 --- a/pc/vgas3.c +++ b/pc/vgas3.c @@ -240,6 +240,7 @@ s3load(VGAscr* scr, Cursor* curs) case 0xE18A: /* ViRGE/[DG]X */ case 0xE110: /* ViRGE/GX2 */ case 0xE13D: /* ViRGE/VX */ + case 0xE112: /* Savage4/MX */ case 0xE122: /* Savage4 */ p += scr->storage; break; @@ -287,6 +288,7 @@ s3load(VGAscr* scr, Cursor* curs) case 0xE18A: /* ViRGE/[DG]X */ case 0xE110: /* ViRGE/GX2 */ case 0xE13D: /* ViRGE/VX */ + case 0xE112: /* Savage4/MX */ case 0xE122: /* Savage4 */ break;