From 8dc045a122c5005adca3007523cac6a1d279c3b8 Mon Sep 17 00:00:00 2001 From: David du Colombier <0intro@gmail.com> Date: Thu, 17 Jul 1997 00:00:00 +0000 Subject: [PATCH] Plan 9 from Bell Labs 1997-07-17 --- pc/memory.c | 6 +-- pc/vgaclgd542x.c | 98 +++++++++++++++++++++++++++++++++++++----------- 2 files changed, 80 insertions(+), 24 deletions(-) diff --git a/pc/memory.c b/pc/memory.c index bfa287938f80bd8fd9c4834ad2610705ff6868b2..bad1023ae77060243773bff374a90280c84f781e 100644 --- a/pc/memory.c +++ b/pc/memory.c @@ -392,14 +392,14 @@ upainit(void) ulong addr, pa, pae, *table, *va, x; /* - * Allocate an 8MB chunk aligned to 16MB. Later can + * Allocate an 64MB chunk aligned to 64MB. Later can * make the region selectable via conf if necessary. */ - if((addr = mapalloc(&rmapupa, 0, 8*MB, 16*MB)) == 0) + if((addr = mapalloc(&rmapupa, 0, 64*MB, 64*MB)) == 0) return; pa = addr; - pae = pa+(16*MB); + pae = pa+(64*MB); while(pa < pae){ va = KADDR(pa); table = &((ulong*)m->pdb)[PDX(va)]; diff --git a/pc/vgaclgd542x.c b/pc/vgaclgd542x.c index ac9cb7d81eec5929ceabb555bb2e3eaf24adff9b..88fd8cbde483d69740960d807ed770e61e56e43e 100644 --- a/pc/vgaclgd542x.c +++ b/pc/vgaclgd542x.c @@ -3,6 +3,7 @@ #include "mem.h" #include "dat.h" #include "fns.h" +#include "io.h" #include "../port/error.h" #include @@ -23,6 +24,44 @@ clgd542xpage(int page) unlock(&clgd542xlock); } +static int +clgd542xlinear(ulong* mem, ulong* size, ulong* align) +{ + ulong baseaddr; + static Pcidev *p; + + if((*size && *size < 16*MB) || (*align && (*align & (16*MB-1)))) + return 0; + + *mem = 0; + + /* + * This obviously isn't good enough on a system with + * more than one PCI card from Cirrus. + */ + if(p == 0 && (p = pcimatch(p, 0x1013, 0)) == 0) + return 0; + + switch(p->did){ + + case 0xA0: + case 0xA8: + case 0xAC: + break; + + default: + return 0; + } + + if((baseaddr = upamalloc(0, *size, *align)) == 0) + return 0; + *mem = baseaddr; + baseaddr = PADDR(baseaddr); + pcicfgw32(p, PciBAR0, baseaddr); + + return *mem; +} + static void disable(void) { @@ -38,6 +77,7 @@ static void enable(void) { uchar sr12; + int mem, x; /* * Disable the cursor. @@ -54,32 +94,45 @@ enable(void) setcolor(0x0F, Pblack<<(32-6), Pblack<<(32-6), Pblack<<(32-6)); vgaxo(Seqx, 0x12, sr12); - /* - * Memory size. The BIOS leaves this in Seq0A, bits 4 and 3. - * See Technical Reference Manual Appendix E1, Section 1.3.2. - * - * The storage area for the 64x64 cursors is the last 16Kb of - * display memory. - */ - switch((vgaxi(Seqx, 0x0A)>>3) & 0x03){ - - case 0: - storage = (256-16)*1024; - break; - - case 1: - storage = (512-16)*1024; + mem = 0; + switch(vgaxi(Crtx, 0x27) & ~0x03){ + + case 0x88: /* CL-GD5420 */ + case 0x8C: /* CL-GD5422 */ + case 0x94: /* CL-GD5424 */ + case 0x80: /* CL-GD5425 */ + case 0x90: /* CL-GD5426 */ + case 0x98: /* CL-GD5427 */ + case 0x9C: /* CL-GD5429 */ + /* + * The BIOS leaves the memory size in Seq0A, bits 4 and 3. + * See Technical Reference Manual Appendix E1, Section 1.3.2. + * + * The storage area for the 64x64 cursors is the last 16Kb of + * display memory. + */ + mem = (vgaxi(Seqx, 0x0A)>>3) & 0x03; break; - case 2: - storage = (1024-16)*1024; + case 0xA0: /* CL-GD5430 */ + case 0xA8: /* CL-GD5434 */ + case 0xAC: /* CL-GD5436 */ + /* + * Attempt to intuit the memory size from the DRAM control + * register. Minimum is 512KB. + * If DRAM bank switching is on then there's double. + */ + x = vgaxi(Seqx, 0x0F); + mem = (x>>3) & 0x03; + if(x & 0x80) + mem++; break; - case 3: - storage = (2048-16)*1024; + default: /* uh, ah dunno */ break; } - + storage = ((256<>16)<<4); p = ((uchar*)gscreen.base) + (storage & 0xFFFF); } - p += index*1024; +// p += index*1024; +memset(p, 0xFF, 16*1024); +return; for(y = yo; y < 16; y++){ p0 = c->clr[2*y]; @@ -225,6 +280,7 @@ static Hwgc clgd542xhwgc = { static Vgac clgd542x = { "clgd542x", clgd542xpage, + clgd542xlinear, 0, };