From 890b91ec1087a88ded8e1884d4f6226ffe284843 Mon Sep 17 00:00:00 2001
From: David du Colombier <0intro@gmail.com>
Date: Tue, 14 Aug 2001 00:00:00 +0000
Subject: [PATCH] Plan 9 from Bell Labs 2001-08-14

---
 bitsy/fns.h   |  3 +++
 bitsy/l.s     | 28 +++++++++++++++++++++++++++-
 bitsy/mem.h   |  2 +-
 bitsy/mmu.c   |  2 +-
 bitsy/power.c | 29 +++++++++++++++++++++++------
 5 files changed, 55 insertions(+), 9 deletions(-)

diff --git a/bitsy/fns.h b/bitsy/fns.h
index 7eb2c8386d51f174f35300d3fcd8ae1bcb29ab86..ed33918d5914d7c9fa256c7631f05fb601646008 100644
--- a/bitsy/fns.h
+++ b/bitsy/fns.h
@@ -30,6 +30,9 @@ char*	getconf(char*);
 ulong	getcpuid(void);
 ulong	getfar(void);
 ulong	getfsr(void);
+ulong	getcontrol(void);
+ulong	getdac(void);
+ulong	getttb(void);
 void*	getlink(void);
 #define	getpgcolor(a)	0
 ulong	getsp(void);
diff --git a/bitsy/l.s b/bitsy/l.s
index 4ed5823bc452a718f2f2184ca30929897f05f606..365f135d52b9d8dab0f63afd123c4f6a076d214f 100644
--- a/bitsy/l.s
+++ b/bitsy/l.s
@@ -134,6 +134,24 @@ TEXT getfsr(SB), $-4
 	MRC	CpMMU, 0, R0, C(CpFSR), C(0x0)
 	RET
 
+/* return mmu control register */
+TEXT getcontrol(SB), $-4
+	SUB R0, R0
+	MRC	CpMMU, 0, R0, C(CpControl), C(0x0)
+	RET
+
+/* return mmu dac register */
+TEXT getdac(SB), $-4
+	SUB R0, R0
+	MRC	CpMMU, 0, R0, C(CpDAC), C(0x0)
+	RET
+
+/* return mmu ttb register */
+TEXT getttb(SB), $-4
+	SUB R0, R0
+	MRC	CpMMU, 0, R0, C(CpTTB), C(0x0)
+	RET
+
 /* return fault address */
 TEXT getfar(SB), $-4
 	MRC	CpMMU, 0, R0, C(CpFAR), C(0x0)
@@ -151,6 +169,10 @@ TEXT mmuenable(SB), $-4
 	MRC	CpMMU, 0, R0, C(CpControl), C(0x0)
 	ORR	$(CpCmmuena|CpCdcache|CpCicache|CpCwb), R0
 	MCR     CpMMU, 0, R0, C(CpControl), C(0x0)
+	MOVW R0, R0
+	MOVW R0, R0
+	MOVW R0, R0
+	MOVW R0, R0
 	RET
 
 TEXT mmudisable(SB), $-4
@@ -564,7 +586,11 @@ TEXT sa1100_power_resume(SB), $-4
 	MOVW	144(R0), R3
 	MCR		CpMMU, 0, R3, C(CpDAC), C(0x0)
 	MOVW	152(R0), R3
-	MCR		CpMMU, 0, R3, C(CpControl), C(0x0)
+	MCR		CpMMU, 0, R3, C(CpControl), C(0x0)	/* Enable cache */
+	MOVW	R0, R0
+	MOVW	R0, R0
+	MOVW	R0, R0
+	MOVW	R0, R0
 	MOVW	156(R0), R3
 	MCR		CpMMU, 0, R3, C(CpFSR), C(0x0)
 	MOVW	160(R0), R3
diff --git a/bitsy/mem.h b/bitsy/mem.h
index c92a3d93dfac073e4c56ef27049ec30bb800517f..45a7e0267191a40b8cf2606c1a72161c1d18c4ee 100644
--- a/bitsy/mem.h
+++ b/bitsy/mem.h
@@ -160,7 +160,7 @@
 #define CpTLBFlush	8		/* W: TLB flushing */
 #define CpRBFlush	9		/* W: Read Buffer ops */
 #define CpPID		13		/* RW: PID for virtual mapping */
-#define	CpBpt		14		/* W: Breakpoint register */
+#define CpBpt		14		/* W: Breakpoint register */
 #define CpTest		15		/* W: Test, Clock and Idle Control */
 
 /*
diff --git a/bitsy/mmu.c b/bitsy/mmu.c
index 49c5a1fdc31744a249dc56b3b809db2fde88e13b..d6af78c3944f61b8eaad6a2075ac07d5f0ce8cf1 100644
--- a/bitsy/mmu.c
+++ b/bitsy/mmu.c
@@ -118,6 +118,7 @@ mmuinit(void)
 void
 mmurestart(void) {
 	/* set up the domain register to cause all domains to obey pte access bits */
+
 	putdac(Dclient);
 
 	/* point to map */
@@ -125,7 +126,6 @@ mmurestart(void) {
 
 	/* enable mmu */
 	wbflush();
-	icacheinvalidate();	/* you never know ... (sape) */
 	mmuinvalidate();
 	mmuenable();
 	cacheflush();
diff --git a/bitsy/power.c b/bitsy/power.c
index 7b2751f3d1af5e6052b7c2a6bca8f6768fb3542b..4f3b8adfeafd40950f61c3daf3b35d15747a23db 100644
--- a/bitsy/power.c
+++ b/bitsy/power.c
@@ -51,6 +51,8 @@ dumpitall(void)
 	iprint("dram: mdcnfg msc %lux %lux %lux mecr %lux\n",
 		memconfregs->msc0, memconfregs->msc1,memconfregs->msc2,
 		memconfregs->mecr);
+	iprint("mmu: CpControl %lux CpTTB %lux CpDAC %lux\n",
+		getcontrol(), getttb(), getdac());
 	iprint("powerregs: pmcr %lux pssr %lux pcfr %lux ppcr %lux pwer %lux pspr %lux pgsr %lux posr %lux\n",
 		powerregs->pmcr, powerregs->pssr, powerregs->pcfr, powerregs->ppcr,
 		powerregs->pwer, powerregs->pspr, powerregs->pgsr, powerregs->posr);
@@ -143,15 +145,23 @@ void
 deepsleep(void) {
 	static int power_pl;
 	ulong xsp, xlink;
+	int i;
+	extern ulong l1table;
 
 	xlink = getcallerpc(&xlink);
+	iprint("l1table at 0x%8.8lux\n", l1table);
+	setpowerlabel();
+	for (i = 0; i < 168/4; i++){
+		if (i % 4 == 0) iprint("\n");
+		iprint("%3d: 0x%8.8lux	", i*4, power_resume[i]);
+	}
 	/* Power down */
 	irpower(0);
 	audiopower(0);
 	screenpower(0);
 	µcpower(0);
 	power_pl = splhi();
-	iprint("entering suspend mode, sp = 0x%lux, pc = 0x%lux, psw = 0x%lux\n", &xsp, xlink, power_pl);
+	iprint("entering suspend mode, sp = 0x%lux, pc = 0x%lux, psw = 0x%lux\n\n", &xsp, xlink, power_pl);
 	dumpitall();
 	delay(100);
 	uartpower(0);
@@ -161,19 +171,19 @@ deepsleep(void) {
 	intrcpy(&savedintrregs, intrregs);
 	cacheflush();
 	delay(50);
-	if (setpowerlabel()) {
+	if(setpowerlabel()){
 		/* Turn off memory auto power */
 		memconfregs->mdrefr &= ~0x30000000;
-		mmurestart();
 		gpiorestore(gpioregs, &savedgpioregs);
 		delay(50);
 		intrcpy(intrregs, &savedintrregs);
-		if (intrregs->icip & (1<<IRQgpio0)){
+		if(intrregs->icip & (1<<IRQgpio0)){
 			// don't want to sleep now. clear on/off irq.
 			gpioregs->edgestatus = (1<<IRQgpio0);
 			intrregs->icip = (1<<IRQgpio0);
 		}
 		trapresume();
+//		mmurestart();
 		clockpower(1);
 		gpclkregs->r0 = 1<<0;
 		rs232power(1);
@@ -191,6 +201,8 @@ deepsleep(void) {
 	}
 	wbflush();
 	delay(50);
+	mmuinvalidate();
+	delay(10);
 	sa1100_power_off();
 	/* no return */
 }
@@ -198,14 +210,19 @@ deepsleep(void) {
 void
 powerkproc(void*)
 {
+	ulong xlink, xlink1;
 
 	for(;;){
 		while(powerflag == 0)
 			sleep(&powerr, powerdown, 0);
 
-		iprint("call deepsleep\n");
+		xlink = getcallerpc(&xlink);
+
+		iprint("call deepsleep, pc = 0x%lux, sp = 0x%lux\n", xlink, &xlink);
 		deepsleep();
-		iprint("deepsleep returned\n");
+		xlink1 = getcallerpc(&xlink1);
+
+		iprint("deepsleep returned, pc = 0x%lux, sp = 0x%lux\n", xlink1, &xlink);
 
 		delay(2000);