From 78098e65064ba6d88184ac77f3d80b1ec4857e8d Mon Sep 17 00:00:00 2001
From: David du Colombier <0intro@gmail.com>
Date: Mon, 11 Dec 2000 00:00:00 +0000
Subject: [PATCH] Plan 9 from Bell Labs 2000-12-11

---
 bitsy/devflash.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/bitsy/devflash.c b/bitsy/devflash.c
index 6b09d0cee598ab4363cb89ae9a320d9ad65a6fb0..d1038afa0c4c64c3ceca21c24eb93be8fc8be688 100644
--- a/bitsy/devflash.c
+++ b/bitsy/devflash.c
@@ -653,15 +653,17 @@ ise_erase(ulong addr)
  *  the flash spec claimes writing goes faster if we use
  *  the write buffer.  We fill the write buffer and then
  *  issue the write request.  After the write request,
- *  subsequent reads will yield the status register or,
- *  since error bits are sticky, another write buffer can
- *  be filled and written.
+ *  subsequent reads will yield the status register.
  *
- *  On timeout, we issue a read status register request so
- *  that the status register can be read no matter how we
- *  exit.
+ *  returns the status, even on timeouts.
  *
- *  returns the status.
+ *  NOTE: I tried starting back to back buffered writes
+ *	without reading the status in between, as the
+ *	flowchart in the intel data sheet suggests.
+ *	However, it always responded with an illegal
+ *	command sequence, so I must be missing something.
+ *	If someone learns better, please email me, though
+ *	I doubt it will be much faster. -  presotto@bell-labs.com
  */
 static ulong
 ise_wbwrite(ulong *p, int n, ulong off, ulong baddr, ulong *status)