From 66ed55a6f5923e3b8ef5c0a050b58fe56c5d0162 Mon Sep 17 00:00:00 2001
From: David du Colombier <0intro@gmail.com>
Date: Tue, 15 Jul 1997 00:00:00 +0000
Subject: [PATCH] Plan 9 from Bell Labs 1997-07-15

---
 pc/etherelnk3.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/pc/etherelnk3.c b/pc/etherelnk3.c
index 7b249f1f984a4209cee92c37123ee445d1f97ecc..12c9f1cfa23a9f6ae2cc1c44f2ea0f0bd244d163 100644
--- a/pc/etherelnk3.c
+++ b/pc/etherelnk3.c
@@ -460,7 +460,7 @@ init905(Ctlr* ctlr)
 	Upd *upd;
 
 	np = 0;
-	for(i = 0; i < 16; i++){
+	for(i = 0; i < 64; i++){
 		bp = updalloc(np);
 		if(ctlr->upqhead == 0)
 			ctlr->upqtail = bp;
@@ -1747,14 +1747,19 @@ etherelnk3reset(Ether* ether)
 		ctlr->dnenabled = 1;
 
 		/*
-		 * Too severe, can use receive busmastering at 100Mbps OK,
-		 * but how to tell which rate is actually being used - the
-		 * 3c905 always seems to have dataRate100 set?
+		 * 10MUpldBug.
+		 * Disabling is too severe, can use receive busmastering at
+		 * 100Mbps OK, but how to tell which rate is actually being used -
+		 * the 3c905 always seems to have dataRate100 set?
+		 * Believe the bug doesn't apply if upRxEarlyEnable is set
+		 * and the threshold is set such that uploads won't start
+		 * until the whole packet has been received.
 		 */
+		ctlr->upenabled = 1;
 		x = eepromdata(port, 0x0F);
-		print("software info 2: %uX\n", x);
-		if(x & 0x01)
-			ctlr->upenabled = 1;
+		//print("software info 2: %uX\n", x);
+		if(!(x & 0x01))
+			outl(port+PktStatus, upRxEarlyEnable);
 
 		if(ctlr->upenabled)
 			init905(ctlr);