~kris/9p

9hist

5281772f43e0574fa0e21858c15711758ebda9d8 — David du Colombier 27 years ago 9bc01c7
Plan 9 from Bell Labs 1999-03-14
6 files changed, 51 insertions(+), 31 deletions(-)

M pc/ether2114x.c
M pc/ether79c970.c
M pc/ether82557.c
M pc/etherelnk3.c
M pc/fns.h
M pc/pci.c
M pc/ether2114x.c => pc/ether2114x.c +32 -28
@@ 873,6 873,7 @@ typephymode(Ctlr* ctlr, uchar* block, int wait)
	ctlr->ttm |= *p<<8;
	debug("mc %4.4uX nway %4.4uX fdx %4.4uX ttm %4.4uX\n",
		mc, nway, ctlr->fdx, ctlr->ttm);
	USED(mc);

	phyx = block[2];
	ctlr->curphyad = ctlr->phy[phyx];


@@ 1247,6 1248,7 @@ debug("sct 0x%uX medium 0x%uX k %d curk %d phy %d\n",
				miir(ctlr, k, 1);
				debug("phy%d: index %d oui %uX reg1 %uX\n",
					x, k, oui, miir(ctlr, k, 1));
				USED(oui);
			}
			ctlr->phy[x] = k;
		}


@@ 1263,52 1265,53 @@ dec2114xpci(void)
{
	Ctlr *ctlr;
	Pcidev *p;
	int cfdd;
	int x;

	p = nil;
	while(p = pcimatch(p, 0x1011, 0)){
		switch(p->did){
		default:
			break;
			continue;

		case 0x0019:		/* 21143 */
			/*
			 * Exit sleep mode.
			 */
			cfdd = pcicfgr32(p, 0x40);
			cfdd &= ~0xc0000000;
			pcicfgw32(p, 0x40, cfdd);
			x = pcicfgr32(p, 0x40);
			x &= ~0xc0000000;
			pcicfgw32(p, 0x40, x);
			/*FALLTHROUGH*/

		case 0x0009:		/* 21140 */
			ctlr = malloc(sizeof(Ctlr));
			/*
			 * bar[0] is the I/O port register address and
			 * bar[1] is the memory-mapped register address.
			 */
			ctlr->port = p->mem[0].bar & ~0x01;
			ctlr->pcidev = p;
			break;
		}

			/*
			 * Some cards (e.g. ANA-6910FX) seem to need the Ps bit
			 * set or they don't always work right after a hardware
			 * reset.
			 */
			csr32w(ctlr, 6, Mbo|Ps);
			softreset(ctlr);
		/*
		 * bar[0] is the I/O port register address and
		 * bar[1] is the memory-mapped register address.
		 */
		ctlr = malloc(sizeof(Ctlr));
		ctlr->port = p->mem[0].bar & ~0x01;
		ctlr->pcidev = p;

			if(srom(ctlr)){
				free(ctlr);
				break;
			}
		/*
		 * Some cards (e.g. ANA-6910FX) seem to need the Ps bit
		 * set or they don't always work right after a hardware
		 * reset.
		 */
		csr32w(ctlr, 6, Mbo|Ps);
		softreset(ctlr);

			if(ctlrhead != nil)
				ctlrtail->next = ctlr;
			else
				ctlrhead = ctlr;
			ctlrtail = ctlr;
		if(srom(ctlr)){
			free(ctlr);
			break;
		}

		if(ctlrhead != nil)
			ctlrtail->next = ctlr;
		else
			ctlrhead = ctlr;
		ctlrtail = ctlr;
	}
}



@@ 1392,6 1395,7 @@ reset(Ether* ether)
	 */
	ctlr->nrdr = Nrde;
	ctlr->ntdr = Ntde;
	pcisetbme(ctlr->pcidev);
	ctlrinit(ether);

	/*

M pc/ether79c970.c => pc/ether79c970.c +3 -1
@@ 446,8 446,10 @@ amd79c970pci(void)
	Pcidev *p;

	p = nil;
	while(p = pcimatch(p, 0x1022, 0x2000))
	while(p = pcimatch(p, 0x1022, 0x2000)){
		amd79c970adapter(&adapter, p->mem[0].bar & ~0x01, p->intl, p->tbdf);
		pcisetbme(p);
	}
}

static int

M pc/ether82557.c => pc/ether82557.c +1 -0
@@ 906,6 906,7 @@ i82557pci(void)
		 * bar[2] is for the flash ROM (1MB).
		 */
		i82557adapter(&adapter, p->mem[1].bar & ~0x01, p->intl, p->tbdf);
		pcisetbme(p);
	}
}


M pc/etherelnk3.c => pc/etherelnk3.c +1 -0
@@ 1396,6 1396,7 @@ tcm59Xpci(void)
			;

		tcmadapter(port, irq, p->tbdf);
		pcisetbme(p);
	}
}


M pc/fns.h => pc/fns.h +1 -0
@@ 82,6 82,7 @@ void	pcihinv(Pcidev*);
Pcidev* pcimatch(Pcidev*, int, int);
Pcidev* pcimatchtbdf(int);
void	pcireset(void);
void	pcisetbme(Pcidev*);
PCMmap*	pcmmap(int, ulong, int, int);
int	pcmspecial(char*, ISAConf*);
void	pcmspecialclose(int);

M pc/pci.c => pc/pci.c +13 -2
@@ 669,7 669,18 @@ pcireset(void)
		pcicfginit();

	for(p = pcilist; p != nil; p = p->list){
		pcr = pcicfgr16(p, PciPSR);
		pcicfgw16(p, PciPSR, pcr & ~0x04);
		pcr = pcicfgr16(p, PciPCR);
		pcr &= ~0x0004;
		pcicfgw16(p, PciPCR, pcr);
	}
}

void
pcisetbme(Pcidev* p)
{
	int pcr;

	pcr = pcicfgr16(p, PciPCR);
	pcr |= 0x0004;
	pcicfgw16(p, PciPCR, pcr);
}