~kris/9p

9hist

37543894c5a7de17185524a6ec2e444751247988 — David du Colombier 27 years ago 6570d4b
Plan 9 from Bell Labs 1999-07-09
4 files changed, 43 insertions(+), 38 deletions(-)

M pc/devlm78.c
M pc/main.c
M port/devproc.c
M port/sysfile.c
M pc/devlm78.c => pc/devlm78.c +24 -26
@@ 230,9 230,10 @@ read_vid(void)
enum
{
	IntelVendID=	0x8086,
	PiixBridgeID=	0x122E,
	Piix3BridgeID=	0x7000,
	Piix4BridgeID=	0x7110,
	PiixID=		0x122E,
	Piix3ID=	0x7000,

	Piix4PMID=	0x7113,		/* PIIX4 power management function */

	PCSC=		0x78,		/* programmable chip select control register */
	PCSC8bytes=	0x01,


@@ 247,31 248,28 @@ readpcilm78(void)
	p = nil;
	while((p = pcimatch(p, IntelVendID, 0)) != nil){
		switch(p->did){
		case PiixBridgeID:
		case Piix3BridgeID:
		case Piix4BridgeID:
			break;
		default:
			continue;
		/* these bridges have pretty easy access to the lm78 */
		case PiixID:
		case Piix3ID:
			pcs = pcicfgr16(p, PCSC);
			if(pcs & 3) {
				/* already enabled */
				miBASE = pcs & ~3;
				return 0;	
			}

			/* enable the chip, use default address 0x50 */
			pcicfgw16(p, PCSC, 0x50|PCSC8bytes);
			pcs = pcicfgr16(p, PCSC);
			miBASE = pcs & ~3;
			return 0;

		/* this bridge uses the SMbus */
		case Piix4PMID:
			return -1:
		}
		break;
	}
	if(p == nil)
		return -1;

	pcs = pcicfgr16(p, PCSC);
	if(pcs & 3) {
		/* already enabled */
		miBASE = pcs & ~3;
		return 0;	
	}

	/* enable the chip, use default address 0x50 */
	pcicfgw16(p, PCSC, 0x50|PCSC8bytes);
	pcs = pcicfgr16(p, PCSC);
	miBASE = pcs & ~3;

	return 0;
	return -1;
}

static void

M pc/main.c => pc/main.c +1 -0
@@ 418,6 418,7 @@ confinit(void)
		if(kpages > (16*MB + conf.npage*sizeof(Page))/BY2PG){
			kpages = (16*MB + conf.npage*sizeof(Page))/BY2PG;
			conf.nimage = 2000;
			kpages += (conf.nproc*KSTACK)/BY2PG;
		}
	} else {
		if(userpcnt < 10) {

M port/devproc.c => port/devproc.c +17 -1
@@ 162,13 162,15 @@ procopen(Chan *c, int omode)
	Proc *p;
	Pgrp *pg;
	Chan *tc;
	int pid;

	if(c->qid.path & CHDIR)
		return devopen(c, omode, 0, 0, procgen);

	p = proctab(SLOT(c->qid));
	pg = p->pgrp;
	if(p->pid != PID(c->qid))
	pid = PID(c->qid);
	if(p->pid != pid)
		error(Eprocdied);

	omode = openmode(omode);


@@ 222,6 224,11 @@ procopen(Chan *c, int omode)
	if(p->state != Dead)
		c->qid.vers = p->pid;

	/* make sure the process slot didn't get reallocated while we were playing */
	coherence();
	if(p->pid != pid)
		error(Eprocdied);

	return devopen(c, omode, 0, 0, procgen);
}



@@ 235,6 242,12 @@ procwstat(Chan *c, char *db)
		error(Eperm);

	p = proctab(SLOT(c->qid));
	if(waserror()){
		qunlock(&p->debug);
		nexterror();
	}
	qlock(&p->debug);

	if(p->pid != PID(c->qid))
		error(Eprocdied);



@@ 243,6 256,9 @@ procwstat(Chan *c, char *db)

	convM2D(db, &d);
	p->procmode = d.mode&0777;

	poperror();
	qunlock(&p->debug);
}

static int

M port/sysfile.c => port/sysfile.c +1 -11
@@ 111,23 111,13 @@ sysfd2path(ulong *arg)

	validaddr(arg[1], arg[2], 1);

	/*
	 * Undomount below may cclose the chan so bump the
	 * reference count to guard against it going to zero
	 * and being freed.
	 */
	c = fdtochan(arg[0], -1, 0, 1);
	if(waserror()) {
		cclose(c);
		nexterror();
	}

	if(c->name == nil)
		snprint((char*)arg[1], arg[2], "<null>");
	else
		snprint((char*)arg[1], arg[2], "%s", c->name->s);

	poperror();
	cclose(c);
	return 0;
}