M carrera/devether.c => carrera/devether.c +5 -2
@@ 739,10 739,13 @@ etherwrite(Chan *c, void *buf, long n, ulong offset)
nexterror();
}
- tsleep(&ctlr->tr, isoutbuf, ctlr, 10000);
+ tsleep(&ctlr->tr, isoutbuf, ctlr, 1000);
- if(!isoutbuf(ctlr))
+ if(!isoutbuf(ctlr)) {
print("ether transmitter jammed\n");
+ reset(ctlr);
+ WR(cr, Rxen);
+ }
else {
p =(Pbuf*)ctlr->tb[ctlr->th];
memmove(p->d, buf, n);
M carrera/l.s => carrera/l.s +13 -22
@@ 12,6 12,8 @@
#define CONST(x,r) MOVW $((x)&0xffff0000), r; OR $((x)&0xffff), r
+#define RDBGSV CONST(0x80020000, R26); MOVW R29, 0(R26); MOVW M(EPC), R27; MOVW R27, 4(R26); MOVW R31, 8(R26)
+
/*
* R4000 instructions
*/
@@ 305,22 307,15 @@ TEXT vector0(SB), $-4
NOOP4
NOOP4
+ RDBGSV
MOVW $utlbmiss(SB), R26
JMP (R26)
TEXT utlbmiss(SB), $-4
-
- CONST ((0xA0090000), R27)
- MOVW M(EPC), R26
- MOVW R26, 0(R27)
- MOVW M(BADVADDR), R26
- MOVW R26, 4(R27)
- MOVW M(CAUSE), R26
- MOVW R26, 8(R27)
- MOVW M(TLBVIRT), R26
- MOVW R26, 12(R27)
- MOVW M(17), R26
- MOVW R26, 16(R27)
+ CONST (MACHADDR, R26) /* R26 = m-> */
+ MOVW 16(R26), R27
+ ADDU $1, R27
+ MOVW R27, 16(R26) /* m->tlbfault++ */
MOVW M(TLBVIRT), R27
WAIT
@@ 392,6 387,7 @@ TEXT vector100(SB), $-4
NOOP4
NOOP4
+ RDBGSV
MOVW $exception(SB), R26
JMP (R26)
@@ 399,6 395,7 @@ TEXT vector180(SB), $-4
NOOP4
NOOP4
+ RDBGSV
MOVW $exception(SB), R26
JMP (R26)
NOP
@@ 750,9 747,6 @@ tas1:
* we avoid using R4, R5, R6, and R7 so gotopc can call us without saving them
*/
TEXT icflush(SB), $-4 /* icflush(virtaddr, count) */
-MOVW $0xA0090008, R10
-MOVW $2001, R9
-MOVW R9, (R10)
MOVW M(STATUS), R10
WAIT
MOVW 4(FP), R9
@@ 782,9 776,6 @@ icflush1: /* primary cache line size is 16 bytes */
WAIT
WAIT
WAIT
-MOVW $0xA0090008, R10
-MOVW $2002, R9
-MOVW R9, (R10)
RET
TEXT dcflush(SB), $-4 /* dcflush(virtaddr, count) */
@@ 805,10 796,10 @@ dcflush1: /* primary cache line size is 16 bytes */
CACHE PI+HI, 0x10(R8)
CACHE PI+HI, 0x20(R8)
CACHE PI+HI, 0x30(R8)
- CACHE PD+HWB, 0x00(R8)
- CACHE PD+HWB, 0x10(R8)
- CACHE PD+HWB, 0x20(R8)
- CACHE PD+HWB, 0x30(R8)
+ CACHE PD+HWBI, 0x00(R8)
+ CACHE PD+HWBI, 0x10(R8)
+ CACHE PD+HWBI, 0x20(R8)
+ CACHE PD+HWBI, 0x30(R8)
SUB $0x40, R9
ADD $0x40, R8
BGTZ R9, dcflush1
M carrera/mem.h => carrera/mem.h +3 -3
@@ 14,7 14,7 @@
#define PGSHIFT 12 /* log(BY2PG) */
#define PGROUND(s) (((s)+(BY2PG-1))&~(BY2PG-1))
-#define MAXMACH 4 /* max # cpus system can run */
+#define MAXMACH 1 /* max # cpus system can run */
#define KSTACK 4096 /* Size of kernel stack */
/*
@@ 95,7 95,7 @@
/*
* Fundamental addresses
*/
-#define MACHADDR 0x8008e000 /* Mach structures */
+#define MACHADDR (KTZERO-MAXMACH*BY2PG) /* warning: rdbg is near here */
#define UREGSIZE 0xA0 /* Sizeof(Ureg)+retpc & ur */
#define MACHP(n) ((Mach *)(MACHADDR+(n)*BY2PG))
@@ 140,7 140,7 @@
#define PTEPERTAB (PTEMAPMEM/BY2PG)
#define STLBLOG 13
#define STLBSIZE (1<<STLBLOG)
-#define KPTELOG 8
+#define KPTELOG 6
#define KPTESIZE (1<<KPTELOG)
#define SEGMAPSIZE 512
M carrera/mmu.c => carrera/mmu.c +7 -27
@@ 6,8 6,6 @@
#include "io.h"
#include "ureg.h"
-Mach machstruct[100];
-
/*
* tlb entry 0 is used only by mmuswitch() to set the current tlb pid.
*/
@@ 182,18 180,16 @@ kfault(Ureg *ur)
void
kmapinval()
{
- int mno, i;
+ int mno, i, curpid;
KMap *k, *next;
- int curpid;
uchar *ktlbx;
-
if(m->kactive == 0)
return;
curpid = PTEPID(TLBPID(tlbvirt()));
- ktlbx = m->ktlbx;
- for(i = TLBROFF; i < NTLB; i++, ktlbx++){
+ ktlbx = m->ktlbx+TLBROFF;
+ for(i = TLBROFF; i < NTLB; i++, ktlbx++) {
if(*ktlbx == 0)
continue;
TLBINVAL(i, curpid);
@@ 206,7 202,6 @@ kmapinval()
kunmap(k);
}
m->kactive = 0;
- m->ktlbnext = TLBROFF;
}
void
@@ 292,30 287,15 @@ putmmu(ulong tlbvirt, ulong tlbphys, Page *pg)
puttlb(entry->virt, entry->phys0, entry->phys1);
ctl = &pg->cachectl[m->machno];
-((ulong*)0xA0090000)[8] = 0x1000;
-((ulong*)0xA0090000)[5] = tlbvirt;
+ if(*ctl == PG_DATFLUSH) {
+ dcflush((void*)pg->va, BY2PG);
+ *ctl = PG_NOFLUSH;
+ }else
if(*ctl == PG_TXTFLUSH) {
-ulong tlb[4];
-extern int gettlbp(ulong, ulong*);
-extern ulong tlbvirt(void);
-((ulong*)0xA0090000)[6] = tlbphys;
-((ulong*)0xA0090000)[7] = pg->va;
-((ulong*)0xA0090000)[8] = 0x2000;
- if(gettlbp((pg->va & ~BY2PG)|TLBPID(tlbvirt()), tlb) < 0){
- print("entry->virt %lux pg->va %lux\n", entry->virt, pg->va);
- panic("icflush not in TLB");
- }
-if(0 && pg->va == 0x19000) {
-print("xx>> virt %lux phys0 %lux phys1 %lux\n", tlb[0],tlb[1],tlb[2]);
-}
icflush((void*)pg->va, BY2PG);
-((ulong*)0xA0090000)[8] = 0x3000;
*ctl = PG_NOFLUSH;
-((ulong*)0xA0090000)[8] = 0x4000;
}
-((ulong*)0xA0090000)[8] = 0x5000;
splx(s);
-((ulong*)0xA0090000)[8] = 0x6000;
}
void
M port/page.c => port/page.c +1 -0
@@ 118,6 118,7 @@ retry:
break;
if(p == 0) {
+print("! ");
p = palloc.head;
memset(p->cachectl, PG_DATFLUSH, sizeof(p->cachectl));
p->color = color;