5 files changed, 28 insertions(+), 14 deletions(-)

M bitsy/devuart.c
M bitsy/l.s
M bitsy/main.c
M bitsy/mmu.c
M port/xalloc.c

@@ 504,4 504,6 @@ serialputs(char *str, int n)
 			;
 		ur->data = *str++;
 	}
+	while((ur->status1 & XmitBusy))
+		;
 }

@@ 235,7 235,7 @@ TEXT splx(SB), $-4
 	MOVW	R1, CPSR
 	RET
 
-TEXT splxpc(SB), $0				/* for iunlock */
+TEXT splxpc(SB), $-4				/* for iunlock */
 	MOVW	R0, R1
 	MOVW	CPSR, R0
 	MOVW	R1, CPSR

@@ 14,12 14,16 @@ Conf conf;
 void
 main(void)
 {
-	int i;
+	/* zero out bss */
+	memset(edata, 0, end-edata);
 
 	iprint("bitsy kernel\n");
 	confinit();
+	iprint("%d pages %lux(%lud) %lux(%lud)\n", conf.npage, conf.base0, conf.npage0, conf.base1, conf.npage1);
 	xinit();
+	iprint("after xinit\n");
 	mmuinit();
+	iprint("after mmuinit\n");
 	delay(100000);
 	exit(1);
 }


@@ 88,7 92,6 @@ probemem(ulong addr)
 		*p = 0;
 	}
 	p = (ulong*)addr;
-	iprint("%lux @ %lux\n", *p, addr);
 	if(*p != addr)
 		return -1;
 	return 0;


@@ 142,9 145,8 @@ confinit(void)
 		conf.base1 = ktop;
 	else
 		iprint("kernel not in allocatable space\n");
-	iprint("%lux-%lux %lux-%lux\n", conf.base0, conf.npage0, conf.base1, conf.npage1);
 
-	/* make npages the right thing */
+	/* make npage the right thing */
 	conf.npage0 = (conf.npage0 - conf.base0)/BY2PG;
 	conf.npage1 = (conf.npage1 - conf.base1)/BY2PG;
 	conf.npage = conf.npage0+conf.npage1;

@@ 63,31 63,40 @@ mmuinit(void)
 {
 	ulong a, e;
 
-	/* set up the domain register to cause all domains to obey pte access bits */
-	putdac(0x55555555);
-
 	/* get a prototype level 1 page */
 	l1table = xspanalloc(BY2PG, 16*1024, 0);
 	memset(l1table, 0, BY2PG);
 
 	/* direct map DRAM */
-	e = conf.base1 + BY2PG*conf.npage2;
+	e = conf.base1 + BY2PG*conf.npage1;
 	for(a = PHYSDRAM0; a < e; a += OneMeg)
 		l1table[a>>20] = L1Section | L1KernelRW |
 				L1Cached | L1Buffered | (a&L1SectBaseMask);
 
+	/* direct map devs */
+	for(a = REGZERO; a < REGTOP; a += OneMeg)
+		l1table[a>>20] = L1Section | L1KernelRW | (a&L1SectBaseMask);
+
 	/* direct map zeros area */
 	for(a = PHYSNULL0; a < PHYSNULL0 + 128 * OneMeg; a += OneMeg)
 		l1table[a>>20] = L1Section | L1KernelRW |
 				L1Cached | L1Buffered | (a&L1SectBaseMask);
 
 	/* direct map flash */
-	for(a = PHYFLASH0; a < PHYFLASH0 + 128 * OneMeg; a += OneMeg)
+	for(a = PHYSFLASH0; a < PHYSFLASH0 + 128 * OneMeg; a += OneMeg)
 		l1table[a>>20] = L1Section | L1KernelRW |
 				L1Cached | L1Buffered | (a&L1SectBaseMask);
 
 	/* map the uart so that we can continue using iprint */
-	uart3regs = mapspecial(UART3REGS, 64);
+//	uart3regs = mapspecial(UART3REGS, 64);
+
+	/* set up the domain register to cause all domains to obey pte access bits */
+	iprint("setting up domain access\n");
+	putdac(0x55555555);
+
+	/* point to map */
+	iprint("setting tlb map %lux\n", (ulong)l1table);
+	putttb((ulong)l1table);
 }
 
 /*


@@ 97,7 106,7 @@ ulong*
 mapspecial(ulong pa, int len)
 {
 	ulong *t;
-	ulong va, i, base, end, off;
+	ulong va, i, base, end, off, entry;
 	int livelarge;
 	ulong* rv;
 


@@ 127,7 136,7 @@ mapspecial(ulong pa, int len)
 
 			/* create a page table and keep going */
 			t = xspanalloc(BY2PG, 1024, 0);
-			memzero(t, BY2PG, 0);
+			memset(t, 0, BY2PG);
 			l1table[va>>20] = L1PageTable | L1Domain0 |
 						(((ulong)t) & L1PTBaseMask);
 		}

@@ 81,6 81,7 @@ xinit(void)
 	conf.base1 = (ulong)KADDR(conf.base1);
 	conf.npage0 = (ulong)KADDR(conf.npage0);
 	conf.npage1 = (ulong)KADDR(conf.npage1);
+iprint("xinit returning\n");
 }
 
 void*


@@ 218,7 219,7 @@ xhole(ulong addr, ulong size)
 
 	if(xlists.flist == nil) {
 		iunlock(&xlists);
-		print("xfree: no free holes, leaked %lud bytes\n", size);
+		iprint("xfree: no free holes, leaked %lud bytes\n", size);
 		return;
 	}