~kris/9p

9hist

129cc78f5e490c8e8c4095d5cdc3ff0e04d23f4b — David du Colombier 32 years ago 6b6e3f0
Plan 9 from Bell Labs 1994-03-05
4 files changed, 12 insertions(+), 11 deletions(-)

M carrera/io.h
M carrera/main.c
M carrera/trap.c
M port/devcons.c
M carrera/io.h => carrera/io.h +1 -0
@@ 10,6 10,7 @@ enum
	Eisaphys	= 0x90000000,	/* IO port physical */
	Devicevirt	= 0xE0000000,
	Dmabase		= 0xE0000000,	
	  R4030ier	= 0xE00000E8,	/* Interrupt enable register */
	  R4030Isr	= 0xE0000204,	/* Interrupt status register */
	  R4030Et	= 0xE000020C,	/* Eisa error type */
	  R4030Rfa	= 0xE000003C,	/* Remote failed address */

M carrera/main.c => carrera/main.c +10 -10
@@ 228,11 228,11 @@ ioinit(int mapeisa)
	 *  Set the 8259 as master with edge triggered
	 *  input with fully nested interrupts.
	 */
	EISAOUTB(Int0ctl, 0x11);		/* ICW1 - edge triggered, master,
						   ICW4 will be sent */
	EISAOUTB(Int0aux, Int0vec);		/* ICW2 - interrupt vector offset */
	EISAOUTB(Int0aux, 0x04);		/* ICW3 - have slave on level 2 */
	EISAOUTB(Int0aux, 0x01);		/* ICW4 - 8086 mode, not buffered */
	EISAOUTB(Int0ctl, 0x11);	/* ICW1 - edge triggered, master,
					   ICW4 will be sent */
	EISAOUTB(Int0aux, Int0vec);	/* ICW2 - interrupt vector offset */
	EISAOUTB(Int0aux, 0x04);	/* ICW3 - have slave on level 2 */
	EISAOUTB(Int0aux, 0x01);	/* ICW4 - 8086 mode, not buffered */

	/*
	 *  Set up the second 8259 interrupt processor.


@@ 240,11 240,11 @@ ioinit(int mapeisa)
	 *  Set the 8259 as master with edge triggered
	 *  input with fully nested interrupts.
	 */
	EISAOUTB(Int1ctl, 0x11);		/* ICW1 - edge triggered, master,
						   ICW4 will be sent */
	EISAOUTB(Int1aux, Int1vec);		/* ICW2 - interrupt vector offset */
	EISAOUTB(Int1aux, 0x02);		/* ICW3 - I am a slave on level 2 */
	EISAOUTB(Int1aux, 0x01);		/* ICW4 - 8086 mode, not buffered */
	EISAOUTB(Int1ctl, 0x11);	/* ICW1 - edge triggered, master,
					   ICW4 will be sent */
	EISAOUTB(Int1aux, Int1vec);	/* ICW2 - interrupt vector offset */
	EISAOUTB(Int1aux, 0x02);	/* ICW3 - I am a slave on level 2 */
	EISAOUTB(Int1aux, 0x01);	/* ICW4 - 8086 mode, not buffered */

	/*
	 *  pass #2 8259 interrupts to #1

M carrera/trap.c => carrera/trap.c +0 -1
@@ 319,7 319,6 @@ intr(Ureg *ur)
	}
	if(cause & INTR2) {
		isr = IO(ulong, R4030Isr);

		if(isr & (1<<5)) {
			audiodmaintr();
			isr &= ~(1<<5);

M port/devcons.c => port/devcons.c +1 -0
@@ 146,6 146,7 @@ panic(char *fmt, ...)

	exit(1);
}

int
pprint(char *fmt, ...)
{