~kris/9p

9hist

055a10f826b3596ad5458be326bc2f84c7a50987 — David du Colombier 25 years ago 3af1f1a
Plan 9 from Bell Labs 2001-04-28
4 files changed, 22 insertions(+), 38 deletions(-)

M bitsy/devuda1341.c
M pc/devvga.c
M pc/i8259.c
M pc/screen.h
M bitsy/devuda1341.c => bitsy/devuda1341.c +14 -23
@@ 44,13 44,15 @@ static int debug = 0;
 * L3 setup and hold times (expressed in µs)
 */
enum {
	L3_DataSetupTime =	1,	/* 190 ns */
	L3_DataHoldTime =		1,	/*  30 ns */
	L3_ModeSetupTime =	1,	/* 190 ns */
	L3_ModeHoldTime =	1,	/* 190 ns */
	L3_ClockHighTime =	1,	/* 100 ns */
	L3_ClockLowTime =		1,	/* 100 ns */
	L3_HaltTime =			1,	/* 190 ns */
	L3_AcquireTime =		1,
	L3_ReleaseTime =		1,
	L3_DataSetupTime =	(190+999)/1000,	/* 190 ns */
	L3_DataHoldTime =		( 30+999)/1000,
	L3_ModeSetupTime =	(190+999)/1000,
	L3_ModeHoldTime =	(190+999)/1000,
	L3_ClockHighTime =	(100+999)/1000,
	L3_ClockLowTime =		(100+999)/1000,
	L3_HaltTime =			(190+999)/1000,
};

/* UDA 1341 Registers */


@@ 199,9 201,9 @@ static void	setreg(char *name, int val, int n);
static void
L3_acquirepins(void)
{
	gpioregs->set = (GPIO_L3_SCLK_o | GPIO_L3_SDA_io);
	gpioregs->direction |=  (GPIO_L3_SCLK_o | GPIO_L3_SDA_io);
	µdelay(2);
	gpioregs->set = (GPIO_L3_MODE_o | GPIO_L3_SCLK_o | GPIO_L3_SDA_io);
	gpioregs->direction |=  (GPIO_L3_MODE_o | GPIO_L3_SCLK_o | GPIO_L3_SDA_io);
	µdelay(L3_AcquireTime);
}

/*


@@ 210,7 212,8 @@ L3_acquirepins(void)
static void
L3_releasepins(void)
{
	gpioregs->direction &= ~(GPIO_L3_SCLK_o | GPIO_L3_SDA_io);
	gpioregs->direction &= ~(GPIO_L3_MODE_o | GPIO_L3_SCLK_o | GPIO_L3_SDA_io);
	µdelay(L3_ReleaseTime);
}

/*


@@ 220,8 223,6 @@ static void
L3_init(void)
{
	gpioregs->altfunc &= ~(GPIO_L3_SDA_io | GPIO_L3_SCLK_o | GPIO_L3_MODE_o);
	gpioregs->set = GPIO_L3_MODE_o;
	gpioregs->direction |= GPIO_L3_MODE_o;
	L3_releasepins();
}



@@ 276,8 277,6 @@ L3_sendbyte(char data, int mode)
{
	int i;

//suspect	L3_acquirepins();

	switch(mode) {
	case 0: /* Address mode */
		gpioregs->clear = GPIO_L3_MODE_o;


@@ 296,14 295,10 @@ L3_sendbyte(char data, int mode)
	for (i = 0; i < 8; i++)
		L3_sendbit(data >> i);

	µdelay(L3_ModeHoldTime);

	if (mode == 0)  /* Address mode */
		gpioregs->set = GPIO_L3_MODE_o;

	µdelay(L3_ModeHoldTime);

//suspect		L3_releasepins();
}

/*


@@ 319,8 314,6 @@ L3_getbyte(int mode)
	char data = 0;
	int i;

//suspect		L3_acquirepins();

	switch(mode) {
	case 0: /* Address mode - never valid */
		break;


@@ 340,8 333,6 @@ L3_getbyte(int mode)

	µdelay(L3_ModeHoldTime);

	L3_releasepins();

	return data;
}


M pc/devvga.c => pc/devvga.c +7 -5
@@ 61,7 61,6 @@ vgastat(Chan* c, char* dp)
static Chan*
vgaopen(Chan* c, int omode)
{
	pprint("vgaopen: pid %d, %d %p\n", up->pid, c->ref, c);
	return devopen(c, omode, vgadir, nelem(vgadir), devgen);
}



@@ 73,8 72,8 @@ vgaclose(Chan*c)
	pprint("vgaclose: pid %d, %d, %p\n", up->pid, c->ref, c);
	scr = &vgascreen[0];
	if (scr && scr->dev && scr->dev->ovlctl) {
		static char *disable = "disable\n";
		pprint("vgaclose: Calling ovlctl (%p) %p\n", scr->dev->ovlctl, disable);
		static char disable[] = "disable\n"; 

		scr->dev->ovlctl(scr, disable, strlen(disable));
	}
}


@@ 387,8 386,11 @@ vgawrite(Chan* c, void* a, long n, vlong off)

	case Qvgaovl:
		scr = &vgascreen[0];
		pprint("vgawrite: Qvgaovl %d (%s)\n", Qvgaovl, scr->dev->name);
		return 0;
		if (scr->dev->ovlwrite == nil) {
			error(Enooverlay);
			break;
		}
		return scr->dev->ovlwrite(scr, a, n, off);

	case Qvgaovlctl:
		scr = &vgascreen[0];

M pc/i8259.c => pc/i8259.c +0 -10
@@ 164,13 164,3 @@ i8259enable(Vctl* v)

	return VectorPIC+irq;
}

void
i8259dump(void)
{
	uchar aux0, aux1;

	aux0 = inb(Int0aux);
	aux1 = inb(Int1aux);
	print("i8269: %ux %2.2ux %2.2ux\n", i8259mask, aux0, aux1);
}

M pc/screen.h => pc/screen.h +1 -0
@@ 69,6 69,7 @@ struct VGAdev {
	void	(*drawinit)(VGAscr*);
	int	(*fill)(VGAscr*, Rectangle, ulong);
	int	(*ovlctl)(VGAscr*, void*, int);
	int	(*ovlwrite)(VGAscr*, void*, int, vlong);
};

struct VGAcur {